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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e45a8b8b48sm1123522a12.20.2025.02.25.04.03.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Feb 2025 04:03:55 -0800 (PST) Message-ID: Date: Tue, 25 Feb 2025 13:03:50 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 10/10] arm64: dts: qcom: sc7280: Add 'global' interrupt to the PCIe RC nodes To: Krishna Chaitanya Chundru , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski Cc: quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250225-qps615_v4_1-v4-10-e08633a7bdf8@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250225-qps615_v4_1-v4-10-e08633a7bdf8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: enBFY_gPZluwFU61fGGViOCLsYimcrPj X-Proofpoint-GUID: enBFY_gPZluwFU61fGGViOCLsYimcrPj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_04,2025-02-25_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 phishscore=0 clxscore=1015 impostorscore=0 mlxlogscore=534 suspectscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250084 On 25.02.2025 10:34 AM, Krishna Chaitanya Chundru wrote: > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > to the host CPUs. This interrupt can be used by the device driver to > identify events such as PCIe link specific events, safety events, etc... > > Hence, add it to the PCIe RC node along with the existing MSI interrupts. > > Signed-off-by: Krishna Chaitanya Chundru > --- The computer tells me this one is wakeup-capable - is this something we are interested in describing for link up? Konrad