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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6433a3d8775sm1137866a12.5.2025.11.13.02.15.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Nov 2025 02:15:56 -0800 (PST) Message-ID: Date: Thu, 13 Nov 2025 11:15:51 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 13/21] drm/msm/adreno: Introduce A8x GPU Support To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-13-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251110-kaana-gpu-support-v2-13-bef18acd5e94@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BvmQAIX5 c=1 sm=1 tr=0 ts=6915afde cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=WeZqmzoOQpb_IxObF4IA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: cOJorfQeNhY7lv9Yklf5118cZG5sTNM6 X-Proofpoint-GUID: cOJorfQeNhY7lv9Yklf5118cZG5sTNM6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEzMDA3NSBTYWx0ZWRfX/2e0DgBiZiap 9m2ksbH/lF3tQM/23Y7JpuGA9cBfDuSrXR+Yl6OfrgT/g4zSIiqlsUdKKoEnc0Ufu85pSQtfVyx v83yFzyk6FK4oWukVs5rebDz+u7UtRKvyHoSs9MbHS2FDugk3bQr8MMBCUKPuk5c+qFxl2U+kj4 O6khnn4hogzkjzLAzrgE+/ZixTGDFWXrMEQWUPCJnR+YZxFNrqP5eyK/zyG/isDcdyh/OnL5JN4 U3inK3P1hj+Y/mTMp7YfjH+U51Rx/APWB7MHruLlvUFBEh+BInn6TuwIBwTfDdx0Qc/4s5YldxI m9XHk8s/98cou7XqdWFTjFcZLDXig+KdMXVSWWhuRGBxqAyfP6kSrbHVUBOh7UyT2F2T1rII1r3 xC8SXZ9G3MxIm/ZluCiEaGoUDTOAfA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-13_01,2025-11-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511130075 On 11/10/25 5:37 PM, Akhil P Oommen wrote: > A8x is the next generation of Adreno GPUs, featuring a significant > hardware design change. A major update to the design is the introduction > of Slice architecture. Slices are sort of mini-GPUs within the GPU which > are more independent in processing Graphics and compute workloads. Also, > in addition to the BV and BR pipe we saw in A7x, CP has more concurrency > with additional pipes. > > From a software interface perspective, these changes have a significant > impact on the KMD side. First, the GPU register space has been extensively > reorganized. Second, to avoid a register space explosion caused by the > new slice architecture and additional pipes, many registers are now > virtualized, instead of duplicated as in A7x. KMD must configure an > aperture register with the appropriate slice and pipe ID before accessing > these virtualized registers. > > This patch adds only a skeleton support for the A8x family. An A8x GPU > support will be added in an upcoming patch. > > Signed-off-by: Akhil P Oommen > --- [...] > +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + u32 val; > + > + val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); There's also a BIT(23) value here which is seemingly never set, but perhaps may come in useful for the bigger GPU > + > + if (a6xx_gpu->cached_aperture == val) > + return; > + > + gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); > + > + a6xx_gpu->cached_aperture = val; > +} > + > +static void a8xx_aperture_aquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) "acquire" > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + > + spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); > + > + a8xx_aperture_slice_set(gpu, pipe, 0); Maybe we can add "unsigned long flags[MAX_NUM_SLICES]" to a6xx_gpu to make the API a little more ergonomic.. but maybe that's too much IDK [...] > + a6xx_gpu->slice_mask = a6xx_llc_read(a6xx_gpu, > + REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL) & GENMASK(3, 0); Please define that field in the XML [...] > +} > + > +static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu) > +{ > + return ffs(a6xx_gpu->slice_mask) - 1; > +} > + > +static inline bool _a8xx_check_idle(struct msm_gpu *gpu) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + > + /* Check that the GMU is idle */ > + if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) > + return false; > + > + /* Check that the CX master is idle */ > + if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) & > + ~A8XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) > + return false; > + > + return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) & > + A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); Odd parenthesis-alignment (couple times in the file), checkpatch usually mumbles at that [...] > + > +void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + uint32_t wptr; > + unsigned long flags; > + > + spin_lock_irqsave(&ring->preempt_lock, flags); > + > + /* Copy the shadow to the actual register */ > + ring->cur = ring->next; > + > + /* Make sure to wrap wptr if we need to */ > + wptr = get_wptr(ring); > + > + /* Update HW if this is the current ring and we are not in preempt*/ > + if (!a6xx_in_preempt(a6xx_gpu)) { > + if (a6xx_gpu->cur_ring == ring) > + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); I think this should use _fenced too, but I guess the preempt detail is just a harmless copypasta [...] > +static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; > + u32 val; > + > + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, > + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); > + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, > + state ? 0x110111 : 0); a840 sets this, a830 sets 0x10111, please confirm which way x2 skews > + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, > + state ? 0x55555 : 0); > + > + gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1); > + gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); !!state [...] > +static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + const struct a6xx_info *info = adreno_gpu->info->a6xx; > + const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; > + unsigned int pipe_id, i; > + unsigned long flags; > + > + for (pipe_id = PIPE_NONE; pipe_id <= PIPE_DDE_BV; pipe_id++) { > + /* We don't have support for LPAC yet */ > + if (pipe_id == PIPE_LPAC) > + continue; This seems arbitrary - one because there are no defines targetting PIPE_LPAC specifcally in the reg lists you shared and two because it would almost certainly not hurt to configure these registers and otherwise not power up the LPAC pipeline > + > + a8xx_aperture_aquire(gpu, pipe_id, &flags); > + > + for (i = 0; regs[i].offset; i++) { > + if (!(BIT(pipe_id) & regs[i].pipe)) > + continue; > + > + if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) > + *gmem_protect = regs[i].value; > + > + gpu_write(gpu, regs[i].offset, regs[i].value); > + } > + > + a8xx_aperture_release(gpu, flags); > + } > + > + a8xx_aperture_clear(gpu); > +} > + > +static int a8xx_cp_init(struct msm_gpu *gpu) > +{ > + struct msm_ringbuffer *ring = gpu->rb[0]; > + u32 mask; > + > + /* Disable concurrent binning before sending CP init */ > + OUT_PKT7(ring, CP_THREAD_CONTROL, 1); > + OUT_RING(ring, BIT(27)); > + > + OUT_PKT7(ring, CP_ME_INIT, 4); > + > + /* Use multiple HW contexts */ > + mask = BIT(0); > + > + /* Enable error detection */ > + mask |= BIT(1); > + > + /* Set default reset state */ > + mask |= BIT(3); > + > + /* Disable save/restore of performance counters across preemption */ > + mask |= BIT(6); > + > + OUT_RING(ring, mask); > + > + /* Enable multiple hardware contexts */ > + OUT_RING(ring, 0x00000003); > + > + /* Enable error detection */ > + OUT_RING(ring, 0x20000000); > + > + /* Operation mode mask */ > + OUT_RING(ring, 0x00000002); Should we include the pwrup reglist from the get-go too? I don't think you used the ones you declared in patch 15 (or at least my ctrl-f can't find the use of it) [...] > +#define A8XX_CP_INTERRUPT_STATUS_MASK_PIPE \ > + (A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFRBWRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB1WRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB2WRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB3WRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFSDSWRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFMRBWRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFVSDWRAP | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_OPCODEERROR | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VSDPARITYERROR | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_REGISTERPROTECTIONERROR | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_ILLEGALINSTRUCTION | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_SMMUFAULT | \ > + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESP | \ kgsl also enables VBIFRESTP(TYPE/READ/LIENT) [...] > + /* Setup GMEM Range in UCHE */ > + gmem_range_min = SZ_64M; this doesn't seem to ever change, you can inline it [...] > +static void a8xx_dump(struct msm_gpu *gpu) > +{ > + DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", > + gpu_read(gpu, REG_A8XX_RBBM_STATUS)); This can be a single line Konrad