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[2003:e4:1f29:1e00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45eaa7da46esm807878f8f.14.2026.05.21.00.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 00:49:08 -0700 (PDT) Date: Thu, 21 May 2026 09:49:06 +0200 From: Thierry Reding To: Aaron Kling Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] arm64: tegra: Add iommu and dma properties for Tegra194 QSPI Message-ID: References: <20260515-tegra194-qspi-iommu-v1-0-57dfb63cd3d6@gmail.com> <20260515-tegra194-qspi-iommu-v1-3-57dfb63cd3d6@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="hpwpf7a3d2mkznnc" Content-Disposition: inline In-Reply-To: --hpwpf7a3d2mkznnc Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH 3/3] arm64: tegra: Add iommu and dma properties for Tegra194 QSPI MIME-Version: 1.0 On Wed, May 20, 2026 at 12:29:49PM -0500, Aaron Kling wrote: > On Wed, May 20, 2026 at 6:49=E2=80=AFAM Thierry Reding wrote: > > > > On Fri, May 15, 2026 at 03:35:29PM -0500, Aaron Kling via B4 Relay wrot= e: > > > From: Aaron Kling > > > > > > Without iommu and dma enabled, flash storage such as the spi-nor on t= he > > > p3668 module times out and cannot complete any transfers. > > > > > > Signed-off-by: Aaron Kling > > > --- > > > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 8 ++++++++ > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra194.dtsi > > > index 1d659454a6f9fe..0e0a20befe9e68 100644 > > > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > > @@ -923,6 +923,10 @@ spi@3270000 { > > > <&bpmp TEGRA194_CLK_QSPI0_PM>; > > > clock-names =3D "qspi", "qspi_out"; > > > resets =3D <&bpmp TEGRA194_RESET_QSPI0>; > > > + iommus =3D <&smmu TEGRA194_SID_GPCDMA_0>; > > > + dma-coherent; > > > + dmas =3D <&gpcdma 5>, <&gpcdma 5>; > > > + dma-names =3D "rx", "tx"; > > > > dmas and dma-names are the only properties that you should need here. >=20 > This is where I started and it didn't work. Without the iommu > properties, I get endless mmu faults upon accessing the qspi flash > device: >=20 > [ 62.313833] tegra-mc 2c00000.memory-controller: axisw: secure write > @0x00000003ffffff00: VPR violation ((null)) > [ 62.324542] arm-smmu 12000000.iommu: Unhandled context fault: > fsr=3D0x402, iova=3D0xcd21d000, fsynr=3D0x80012, cbfrsynra=3D0x820, cb=3D1 >=20 > I know downstream kernels aren't always (normally...) the arbiter of > sanity, but I did pull these from the Nvidia downstream 5.10 kernel, > which is where Nvidia was starting to try to align with mainline > paradigms. All of these properties are set there. >=20 > If the qspi node isn't supposed to set iommu directly, then there's a > larger problem here that I don't even know where to begin to look > into. All I can say is that dma fails with faults if they are not set > and works when they are. I think this is a problem similar to what we experienced with I2C a little while ago, which we fixed like so: cdbf26251d3b ("i2c: tegra: Allocate DMA memory for DMA engine") There's another patch currently under review that tries to simplify this further using new support from the dmaengine subsystem: https://patchwork.ozlabs.org/project/linux-tegra/patch/20260518114013.6= 2065-2-akhilrajeev@nvidia.com/ Doing something analogous for QSPI should fix this. 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