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Tue, 12 May 2026 11:10:10 +0800 (CST) Date: Tue, 12 May 2026 11:10:09 +0800 From: Peter Chen To: sashiko@lists.linux.dev Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Subject: Re: [PATCH 4/4] arm64: dts: cix: add Sky1 USB4 and USB5 controllers Message-ID: References: <20260511024244.981941-5-peter.chen@cixtech.com> <20260511235922.10315C2BCB0@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260511235922.10315C2BCB0@smtp.kernel.org> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C7:EE_|KL1PR0601MB5549:EE_ X-MS-Office365-Filtering-Correlation-Id: 200f9507-7816-4633-758d-08deafd3fc19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|18002099003|22082099003|3023799003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IEp7ZktDzYS31hWvKYQMbNcD3LS4N49R+m4YIsSLgrA6ehp9bDvk/UOqVfp1+UuRaVNYuaLGbe9iyWJOJh4kEeJ2d+eVwH0aXzva5OtBTZ/C/pRfaDiWumLhfygBjjT1MUKYRmE0sZD7TR+w3yQVC9H1eQUsV61Q/GvdLbrBz5+cWdXeTOxGJKvgOfHWU5zRZAx3yrGfOtHlu9vnB1j9tVuAEAHF/nG3ynsgx2j2f46G2EhkYZoszt00pEHlq6Fx6I9hZEqlAFdfx2KHp7aOW5B0gK23h9JlNRSvOIaCdkAAejIUxfKTdY5czXzzlmPgo2AB3G0B+vsY/56tJqOKpqqy4ITJoxLrSO3s9ZlBpJQo/8yHP+XaO2kV1WhiErFrxp6M+xG88nCY4qsWmdY6gAAx7KmfhZt2UpcmSsGEL+BTxwazEzqHDXk8T+dmUOaS X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2026 03:10:12.9818 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 200f9507-7816-4633-758d-08deafd3fc19 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR0601MB5549 On 26-05-11 23:59:21, sashiko-bot@kernel.org wrote: > EXTERNAL EMAIL > > Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider: > - [Medium] Missing `status = "disabled";` for `usb4` and `usb5` device nodes in the SoC-level device tree. Ack > - [Medium] Invalid double-vendor prefix in compatible string and squashing of SoC-specific glue layer with generic IP core. Nak > - [Low] Unnecessary inclusion of `` in `sky1.dtsi` without associated PHY definitions. Ack > - [Low] Redundant/duplicate interrupt mappings for the `wakeup` interrupt. Nak > -- > > commit a270480764c96a27fe2e14e30bfb46b99527fcfb > Author: Peter Chen > > arm64: dts: cix: add Sky1 USB4 and USB5 controllers > > Add the Sky1 USB4 and USB5 Cadence USB3 controller nodes with their > registers, interrupts, clocks, resets and S5 syscon control. Enable both > ports on the Orion O6 board in host mode with the required VBUS pinctrl. > > > diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi > > index bb5cfb1f21133..9f7d9ad6586c3 100644 > > --- a/arch/arm64/boot/dts/cix/sky1.dtsi > > +++ b/arch/arm64/boot/dts/cix/sky1.dtsi > > @@ -6,6 +6,8 @@ > > > > #include > > #include > > +#include > > Since there are no phys properties or macros from this header used in the > patch, is this inclusion needed? Ack, will delete. > > > +#include > > #include "sky1-power.h" > > > > / { > > [ ... ] > > > @@ -504,6 +506,72 @@ mbox_ap2sfh: mailbox@80a0000 { > > cix,mbox-dir = "tx"; > > }; > > > > + usb4: usb@91d0000 { > > + compatible = "cix,sky1-usb3", "cix,cdns-usb3"; > > Does the "cix,cdns-usb3" string incorrectly combine two vendor prefixes? > Should the generic fallback be "cdns,usb3"? No. sky1-usb for specific SoCs "sky1", "cdns-usb3" for general CIX SoCs using Cadence IP. > > > + reg = <0x00 0x91d0000 0x00 0x4000>, > > + <0x00 0x91d4000 0x00 0x4000>, > > + <0x00 0x91d8000 0x00 0x8000>, > > + <0x00 0x91c0314 0x00 0x4>; > > + reg-names = "otg", "dev", "xhci", "glue"; > > Does adding the "glue" register and cix,syscon-usb to the generic core > break the generic upstream schema which expects only three reg entries? > > Should the SoC-specific glue logic be implemented as a parent wrapper node > with a child node for the generic Cadence USB3 core instead? For sky1 USB, it uses Cadence USB3 core as library, so all register regions need pass from one parent node. > > > + > > + interrupts = , /* host irq */ > > + , /* peripheral irq */ > > + , /* otgirq */ > > + ; /* wakeup irq */ > > The wakeup interrupt uses the same GIC SPI line as the main host and > peripheral interrupts. Is this redundant, and could it lead to conflicting > interrupt registration? > Not redundant, they are different interrupt handlers and knows itself at code. > [ ... ] > > > + cix,syscon-usb = <&s5_syscon>; > > + dma-coherent; > > + maximum-speed = "super-speed-plus"; > > + dr_mode = "otg"; > > + }; > > Should this node include a status = "disabled" property so the USB drivers do > not probe unconditionally on all boards using this SoC? Ack -- Best regards, Peter