From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BE653AB29B; Tue, 12 May 2026 20:13:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778616831; cv=none; b=UTAtGGb44pGssaMUyic4F6Q64Wdlr3pKfkPFWAPtPn9HQNtVv+colcoD8Pf9v44E+Sab4/S8u/1E6RuhBmXSjQdudjOLh96HmcAp8HNRcSPZ00Uk+jfsSsYNC55q3b1JqdejXZLtQGYh5ghDh7xZZhJQP0Y6gDG1MSDQ290WyEo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778616831; c=relaxed/simple; bh=XvB3gabDoBtEZDsoQE+oOCgIII/QrOVRQO8RyhFRouM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FFODBaJ0cWHgVxGa89VaxIrokJpIgC3mlFX/VVnQNjSU5fLPmsOUlsmAetPT444ozHFnP8pODH78D3xwmJ6RYc0q5PlxDyla5+C8ONzYsx+CIzz2U0D+/aG2JcLg9tIR25RcN0GL0Tehsxc5X76G5HyKcZQ3TVJYvstHrZqumbI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ipbr2QOB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ipbr2QOB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 019D5C2BCB0; Tue, 12 May 2026 20:13:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778616830; bh=XvB3gabDoBtEZDsoQE+oOCgIII/QrOVRQO8RyhFRouM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ipbr2QOBXC73RkC+UYQpb8prJLPRYxG4rD8FmmM01iI/XOR6Id90XPw+sgjk06rd1 dNCZ1Hcyp73yMvqYzM5jPzBRQxOM9vTep0KZ/MdNowC+vHcL+6FKwxWTojXlWJPc6T 0mqoHV9sr6Y7osZIv9v/rgBMnApnPqx6rauMP1MlWzS9b40447Gg/08cWvS22/I4f3 kfUgnkOvBvkV9cLEo85Kx/tj/yg1PABSasFr7LM6xmprJmWTrbIQ6hvkSnGDIPoBG6 aDi3wYY8O9Fh3Jf/Tv+E/fJ9zwpHugl2bPG+/vESfcQ0WkNKwHBTcNHWFsuadsi2L+ c5AiMjZ4r+blQ== Date: Tue, 12 May 2026 15:13:46 -0500 From: Bjorn Andersson To: Taniya Das Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa Subject: Re: [PATCH v4] arm64: dts: qcom: sm8750: Add camera clock controller Message-ID: References: <20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com> On Mon, May 11, 2026 at 03:45:43PM +0530, Taniya Das wrote: > The camera clock controller is split into cambistmclk and camcc. The > cambist clock controller handles the mclks and the rest of the clocks of > camera are part of the camcc clock controller. > Add the camcc clock controller device node for SM8750 SoC. > > Reviewed-by: Abel Vesa > Signed-off-by: Taniya Das > --- > Changes in v4: > - Fix Stray space before the ',' in cambistcc node [Konrad] > - Link to v3: https://lore.kernel.org/r/20260225-sm8750_camcc_dt-v3-1-a19d3173a160@oss.qualcomm.com > > Changes in v3: > - Update the Mx phandle to use MXC for camcc node as it is a always ON > rail and can sustain this usecase. > - Link to v2: https://lore.kernel.org/r/20260220-sm8750_camcc_dt-v2-1-e4b7faf35854@oss.qualcomm.com > > Changes in v2: > - Update the MxC phandle to use MX for camcc node. > - Add RB tag [Abel Vesa] and update the commit message. > - Link to v1: https://lore.kernel.org/r/20251203-sm8750_camcc_dt-v1-1-418e65e0e4e8@oss.qualcomm.com > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 37 +++++++++++++++++++++++++++++++++++- > 1 file changed, 36 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index 3f0b57f428bbb388521c27d9ae96bbef3d62b2e2..dabff4518867df88d8e4cdc233ef6325635b7ae9 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -2,7 +2,8 @@ > /* > * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > - > +#include > +#include I had to fix the sort order, but the merge conflict tells me that you didn't rebase this on v7.1-rc1 (or later). Regards, Bjorn > #include > #include > #include > @@ -2046,6 +2047,23 @@ aggre2_noc: interconnect@1700000 { > clocks = <&rpmhcc RPMH_IPA_CLK>; > }; > > + cambistmclkcc: clock-controller@1760000 { > + compatible = "qcom,sm8750-cambistmclkcc"; > + reg = <0x0 0x1760000 0x0 0x6000>; > + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MX>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > mmss_noc: interconnect@1780000 { > compatible = "qcom,sm8750-mmss-noc"; > reg = <0x0 0x01780000 0x0 0x5b800>; > @@ -2740,6 +2758,23 @@ usb_dwc3_ss: endpoint { > }; > }; > > + camcc: clock-controller@ade0000 { > + compatible = "qcom,sm8750-camcc"; > + reg = <0x0 0xade0000 0x0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8750-pdc", "qcom,pdc"; > reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; > > --- > base-commit: 47b7b5e32bb7264b51b89186043e1ada4090b558 > change-id: 20251203-sm8750_camcc_dt-350a8d217376 > > Best regards, > -- > Taniya Das >