> > It just so happens that at the same time as you submitting this, Marek
> > Vasut wants to enable shared write-protect GPIOs for EEPROMs. This
> > seems to be a similar situation where the default is to keep the line
> > high and drive it low if there's at least one consumer that wants it.
> > I will rework the gpio-shared-proxy driver with that logic in mind.
> > Would that be enough to address the issue here?
> 
> I'm unsure if this helps. From my understanding SCL gets toggled 
> high/low for each transferred bit during an operation. This data block 
> may not be intercepted by other consumers

I agree. SCL is shared between the busses but if one bus uses it, the
bus needs exclusive access to generate the desired clock rate. The other
busses have to wait until the on-going transfer is over. This is
different from the shared-GPIO examples Bart gave which need all the
input ANDed together which would result in a chaos clock rate here.

But thanks for the explanations, Bart!