From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E715A3C7E13; Sun, 17 May 2026 17:35:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779039339; cv=none; b=et9HPCidEtJyE1egkhES3Dvvh3nee/clhe+9GViOR4fwCjPh1dv06P0upkUg/G7v7NdE+pPXK/guHyE3mf9bI8MkXn0AQDul0ZLKjBHKXCItGr3Z0cxDjM83pny/0P4mlaJS5wDJlc+IxEBoKVtS+RgKbwj1OLsuSVi0bssBdXw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779039339; c=relaxed/simple; bh=kHEmJEsLgjrrwfX1LtaGf01yk3PATkzVpCn7a91Gql0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=S3I/wE8OSjLs6k+R1mbJZQbYRbANB3KrZ2lDn+f1JmEwKhgSt64vTPV/aXob+6gK0PpgxrKP6A+Aoxbu5RIjSrVnNXbFXPCL6XYgoOP2IcoPcYYN4Kz4BUagDJppdYNx3uHR5bhBHEiCfKbqggBETDQ+Wc5PZvbecXZQtaT5huE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W+dsyEp9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W+dsyEp9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11B6BC2BCB0; Sun, 17 May 2026 17:35:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779039338; bh=kHEmJEsLgjrrwfX1LtaGf01yk3PATkzVpCn7a91Gql0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=W+dsyEp90fD12YbOY4YALF7F/baFhWY0GpNZGya6zkNeXLopP1G2hksI8cmqIm5yV /VB7prgURakNbtRyyeHp7YHrfhUKIVF+f0v4DXsH7x+wi1JJfG17qU79DFNGdBCTN7 nk2bmHPlG69nrca9QQhvbjOUaa/F8jI4gG6Czke1mF7d4+V0ywwNJzVbG+QQoD/x8L q1FHHH2ATWfkcPCuLtQXfBBv6yKdMa+RDp8vULZHHk10+3nEfqHQTOJ+PB/cCgzhkx ErIVcI9RwQ4bN82d9sGs55Tih7MSwjI6QJHOPh5Kgb1u14+0N5o7yRUfmE88G14MzK GJ3Kq1ENDdsTg== Date: Sun, 17 May 2026 19:35:35 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Mikko Perttunen Cc: Thierry Reding , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yi-Wei Wang Subject: Re: [PATCH v4 4/7] pwm: tegra: Parametrize enable register offset Message-ID: References: <20260331-t264-pwm-v4-0-c041659677cf@nvidia.com> <20260331-t264-pwm-v4-4-c041659677cf@nvidia.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="fopyhq2p3v2ldjwm" Content-Disposition: inline In-Reply-To: <20260331-t264-pwm-v4-4-c041659677cf@nvidia.com> --fopyhq2p3v2ldjwm Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v4 4/7] pwm: tegra: Parametrize enable register offset MIME-Version: 1.0 Hello, On Tue, Mar 31, 2026 at 11:12:16AM +0900, Mikko Perttunen wrote: > On Tegra264, the PWM enablement bit is not located at the base address > of the PWM controller. Hence, introduce an enablement offset field in > the tegra_pwm_soc structure to describe the offset of the register. >=20 > Co-developed-by: Yi-Wei Wang > Signed-off-by: Yi-Wei Wang > Signed-off-by: Mikko Perttunen > --- > drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- > 1 file changed, 12 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c > index 358c81cea05b..b925ef914411 100644 > --- a/drivers/pwm/pwm-tegra.c > +++ b/drivers/pwm/pwm-tegra.c > @@ -61,6 +61,7 @@ > =20 > struct tegra_pwm_soc { > unsigned int num_channels; > + unsigned int enable_reg; > }; > =20 > struct tegra_pwm_chip { > @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, > err =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); > if (err) > return err; > - } else > + } else if (pc->soc->enable_reg =3D=3D PWM_CSR_0) { > val |=3D PWM_ENABLE; > + } > =20 > pwm_writel(pwm, PWM_CSR_0, val); > =20 The patch is a bit artificial because we don't have a driver yet where `pc->soc->enable_reg =3D=3D PWM_CSR_0` doesn't hold. But it looks strange to me that there is no enable bit set for the pc->soc->enable_reg !=3D PWM_CSR_0 case. So I tend to want these changes in squashed into another patch such that the combined patch handles the enabling completely. > @@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, > =20 > static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pw= m) > { > + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); > int rc =3D 0; > u32 val; > =20 > @@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, = struct pwm_device *pwm) > if (rc) > return rc; > =20 > - val =3D pwm_readl(pwm, PWM_CSR_0); > + A single empty line is enough. > + val =3D pwm_readl(pwm, pc->soc->enable_reg); > val |=3D PWM_ENABLE; > - pwm_writel(pwm, PWM_CSR_0, val); > + pwm_writel(pwm, pc->soc->enable_reg, val); > =20 > return 0; > } > =20 > static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *= pwm) > { > + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); > u32 val; > =20 > - val =3D pwm_readl(pwm, PWM_CSR_0); > + val =3D pwm_readl(pwm, pc->soc->enable_reg); > val &=3D ~PWM_ENABLE; > - pwm_writel(pwm, PWM_CSR_0, val); > + pwm_writel(pwm, pc->soc->enable_reg, val); > =20 > pm_runtime_put_sync(pwmchip_parent(chip)); > } > @@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(= struct device *dev) > =20 > static const struct tegra_pwm_soc tegra20_pwm_soc =3D { > .num_channels =3D 4, > + .enable_reg =3D PWM_CSR_0, > }; > =20 > static const struct tegra_pwm_soc tegra186_pwm_soc =3D { > .num_channels =3D 1, > + .enable_reg =3D PWM_CSR_0, > }; > =20 > static const struct of_device_id tegra_pwm_of_match[] =3D { >=20 > --=20 > 2.53.0 >=20 --fopyhq2p3v2ldjwm Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEP4GsaTp6HlmJrf7Tj4D7WH0S/k4FAmoJ/GQACgkQj4D7WH0S /k7AXAf9H6sDXDLbM7hNb9vHT/+s485HnqhOSAaKKX1VVNSmPUj6Ztoc1CRBm5J5 VZd81QDJODnImcgs/Vvp65fFaEYlGUmRJnOToOsRnKLC2Qwet7AzRaFFjEjm76RT n4hJHObg8jgV8l16NPLh+3e/UjAmCfdBqcND32OvZlSexQL0Wh9XvesTHFLu8ad0 SfsG5YwBFa06DY3mI6LnzPhamiumyl2X2zRr5gBYdeZwZlJcMtQJs8+BjmGpDZNX BYy3T96DblJc/2O20K2+7EftoTRino+pqyJ0mSccct3WwvI9bDZAi+84FGh+xAyM YgXMceNQ8/TOBVejTDfLbzVcJt/eUQ== =NMnW -----END PGP SIGNATURE----- --fopyhq2p3v2ldjwm--