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[2003:e4:1f29:1e00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45eb6c9f548sm3620523f8f.2.2026.05.22.03.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 03:32:22 -0700 (PDT) Date: Fri, 22 May 2026 12:32:20 +0200 From: Thierry Reding To: Akhil R Cc: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Laxman Dewangan , Philipp Zabel , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li Subject: Re: [PATCH v6 06/10] dmaengine: tegra: Support address width > 39 bits Message-ID: References: <20260331102303.33181-1-akhilrajeev@nvidia.com> <20260331102303.33181-7-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="cevphyjvhbnvt5ow" Content-Disposition: inline In-Reply-To: <20260331102303.33181-7-akhilrajeev@nvidia.com> --cevphyjvhbnvt5ow Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v6 06/10] dmaengine: tegra: Support address width > 39 bits MIME-Version: 1.0 On Tue, Mar 31, 2026 at 03:52:59PM +0530, Akhil R wrote: > Tegra264 supports address width of 41 bits. Unlike older SoCs which use > a common high_addr register for upper address bits, Tegra264 has separate > src_high and dst_high registers to accommodate this wider address space. >=20 > Add an addr_bits property to the device data structure to specify the > number of address bits supported on each device and use that to program > the appropriate registers. >=20 > Update the sg_req struct to remove the high_addr field and use > dma_addr_t for src and dst to store the complete addresses. Extract > the high address bits only when programming the registers. >=20 > Signed-off-by: Akhil R > Reviewed-by: Frank Li > --- > drivers/dma/tegra186-gpc-dma.c | 83 +++++++++++++++++++++------------- > 1 file changed, 52 insertions(+), 31 deletions(-) Sorry for not noticing this earlier. My understanding is that previously this IP (along with most others) did support 40 bit addressing. That's a much more natural boundary, too. The reason why 39 is often mentioned in this context is that bit 39 was treated specially and interpreted by the memory controller as a way to swizzle memory between the Tegra and discrete GPU formats. I assume GPC DMA was in the same category. I'd be very surprised if there really was a limit on exactly 39 bits. Looking at the register documentation, I see that the high address register is 8 bits, which together with the 32 bits from the regular ADR register gives 40 bits. Given the above this patch looks wrong. Technically the previous iterations did support the full 40 bits, and that should be reflected in the DMA mask. The platform-specific 39-bit restriction due to the swizzle bit is something that we've always represented via the dma-ranges property, but it doesn't reflect the capabilities of the hardware. It's a bit odd that GPC DMA on Tegra264 supports 41 bits. I think the regular address map is only 40 bits, but I guess if the registers define it this way, might as well support it. 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