From: Stephan Gerhold <stephan.gerhold@linaro.org>
To: Maulik Shah <maulik.shah@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thomas Gleixner <tglx@kernel.org>,
Linus Walleij <linusw@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-gpio@vger.kernel.org,
Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Subject: Re: [PATCH v2 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper
Date: Tue, 26 May 2026 14:34:46 +0200 [thread overview]
Message-ID: <ahWTZj727RCNZPR9@linaro.org> (raw)
In-Reply-To: <20260526-hamoa_pdc-v2-3-f6857af1ce91@oss.qualcomm.com>
On Tue, May 26, 2026 at 04:24:39PM +0530, Maulik Shah wrote:
> pdc->enable_intr() function already points to respective version
> specific enable function. pdc_enable_intr() now only kept as wrapper.
> Remove the wrapper and invoke pdc->enable_intr() from caller.
>
> Locking in pdc_enable_intr() applies lock to all pdc->enable_intr()
> however its only required for pdc_enable_intr_bank() which uses
> a shared bank across all interrupts. pdc_enable_intr_cfg() do not
> required locking as IRQ_CFG registers are one per interrupt. Move
> locking accordingly.
Well, pdc_enable_intr_cfg() is still a read-modify-write. If two CPUs
read IRQ_i_CFG at the same time and modify different bits (e.g. enable
and type bits) then write back the modified register one of the
modifications will get lost. Can we be sure that this won't happen?
Perhaps we can since PDC has IRQCHIP_SET_TYPE_MASKED, but personally
I would keep the lock there to be sure, especially with the new GPIO
operations you add that also read-modify-write the same register..
Thanks,
Stephan
next prev parent reply other threads:[~2026-05-26 12:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 10:54 [PATCH v2 0/8] x1e80100: Enable PDC wake GPIOs and deepest idle state Maulik Shah
2026-05-26 10:54 ` [PATCH v2 1/8] irqchip/qcom-pdc: restructure version support Maulik Shah
2026-05-26 10:54 ` [PATCH v2 2/8] irqchip/qcom-pdc: Move all statics to struct pdc_desc Maulik Shah
2026-05-26 10:54 ` [PATCH v2 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper Maulik Shah
2026-05-26 12:34 ` Stephan Gerhold [this message]
2026-05-26 10:54 ` [PATCH v2 4/8] irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI Maulik Shah
2026-05-26 10:54 ` [PATCH v2 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode Maulik Shah
2026-05-26 12:22 ` Stephan Gerhold
2026-05-26 10:54 ` [PATCH v2 6/8] pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller Maulik Shah
2026-05-26 10:54 ` [PATCH v2 7/8] Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" Maulik Shah
2026-05-26 10:54 ` [PATCH v2 8/8] arm64: dts: qcom: x1e80100: Add deepest idle state Maulik Shah
2026-05-26 11:59 ` [PATCH v2 0/8] x1e80100: Enable PDC wake GPIOs and " Stephan Gerhold
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