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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282374300sm7278706b3a.20.2026.06.04.04.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2026 04:28:45 -0700 (PDT) Date: Thu, 4 Jun 2026 16:58:38 +0530 From: Varadarajan Narayanan To: Konrad Dybcio Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: dts: qcom: ipq5210: Enable PCIe support Message-ID: References: <20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com> <20260514-pci-ipq5210-v1-2-a09436200b35@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: 2jBuvsYCIYysAXOFr9xRqejmy-I9oFJf X-Proofpoint-GUID: 2jBuvsYCIYysAXOFr9xRqejmy-I9oFJf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA0MDExMSBTYWx0ZWRfX8ImfnAF7Q0mH 24/2UJYTpQejB9xjxdXgjgd+5ZeOrb2YHrMRI4ZDDo/HrXfGSbr0RDG3feo4QUoJVLl2IR4dmqW srkMhz3FgZPmutiY3ogMb3/8teKKnkyeIhDhpN5IeOaeiugPJW9xN14wx/4udGel34sv15gH6C0 W3jrM4joliiXnnlzO30L0P6s2GYWqonhpb9qpkxB8mibakfAnIrlLk5E15tFo3ev7vPez+w2X9T vWoOgN7blLmenwtZyHAwigOMU0oW0kE7AUEZLLnFJmTuE6oSJJASXaB2e6X9st+s4A056X8DyM/ Ud8dUDsnRyfcM/FYgDLnorZ2ERwLUIqe8+oxnX+utcIRmzDi6Hx10kjmak55i2zOkfdLdvA881m TyC6VBFh6HdXOO3Ve2K4TpPZRzZGjywCnbdDKFrmWTL7wtZ7GENN8rv7S6j6GEue7HHSKQA3m3p Wk5nX70W1gXnSXZ6dJw== X-Authority-Analysis: v=2.4 cv=f4p4wuyM c=1 sm=1 tr=0 ts=6a21616f cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=XMczTv2Me4NSQKEp8ncA:9 a=CjuIK1q_8ugA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-04_03,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606040111 On Fri, May 22, 2026 at 02:24:45PM +0200, Konrad Dybcio wrote: > On 5/14/26 6:13 AM, Varadarajan Narayanan wrote: > > Add DT entries to enable the PCIe controllers found in ipq5210. > > > > Signed-off-by: Varadarajan Narayanan > > --- > > [...] > > > &tlmm { > > + pcie0_default_state: pcie0-default-state { > > + pins = "gpio32"; > > + function = "gpio"; > > + drive-strength = <6>; > > + bias-pull-down; > > + output-low; > > + }; > > + > > + pcie1_default_state: pcie1-default-state { > > + pins = "gpio29"; > > + function = "gpio"; > > + drive-strength = <6>; > > + bias-pull-down; > > + output-low; > > You shouldn't need output-low in either of these definitions (+ sorting > by GPIO idx would be extra neat) Ok. > [...] > > > clocks { > > + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <250000000>; > > + #clock-cells = <0>; > > + }; > > + > > + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <250000000>; > > + #clock-cells = <0>; > > + }; > > Why do these exist? Just pass the QMPPHY reference straight to GCC Ok. > [...] > > > + pcie0_phy: phy@84000 { > > + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy", > > + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > > + reg = <0x0 0x00084000 0x0 0x1000>; > > + > > + clocks = <&gcc GCC_PCIE0_AUX_CLK>, > > + <&gcc GCC_PCIE0_AHB_CLK>, > > + <&gcc GCC_PCIE0_PIPE_CLK>; > > + clock-names = "aux", "cfg_ahb", "pipe"; > > + > > + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; > > + assigned-clock-rates = <20000000>; > > Is this clock supposed to be fixed at that rate, regardless of the link > speed? And is the default rate incorrect? Will drop this. > > + > > + resets = <&gcc GCC_PCIE0_PHY_BCR>, > > + <&gcc GCC_PCIE0PHY_PHY_BCR>; > > + reset-names = "phy", "common"; > > + > > + #clock-cells = <0>; > > + clock-output-names = "gcc_pcie0_pipe_clk_src"; > > Having a gcc_ prefix here smells fishy.. Followed what was used in ipq9574, ipq5424 etc. Will remove gcc_ & _src. > [...] > > > + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, > > + <&gcc GCC_PCIE1_AXI_S_CLK>, > > + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, > > + <&gcc GCC_PCIE1_RCHNG_CLK>, > > + <&gcc GCC_PCIE1_AHB_CLK>, > > + <&gcc GCC_PCIE1_AUX_CLK>; > > + > > + clock-names = "axi_m", > > stray \n above, also in resets Ok. > [...] > > > + pcie1_rp: pcie@0 { > > pcie1_port0 for consistency with other DTs, please > > Same comments for the other port Ok. Thanks Varada