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Thu, 25 Jun 2026 23:13:52 -0700 (PDT) X-Received: by 2002:a05:7300:1488:b0:30b:ff0d:1efa with SMTP id 5a478bee46e88-30c84d9b4c8mr4532498eec.24.1782454431566; Thu, 25 Jun 2026 23:13:51 -0700 (PDT) Received: from oss.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c9c456cf5sm3782007eec.2.2026.06.25.23.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 23:13:51 -0700 (PDT) Date: Fri, 26 Jun 2026 11:43:43 +0530 From: Mohd Ayaan Anwar To: Loic Poulain Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Bjorn Andersson , Konrad Dybcio , Wasim Nazir , Mohd Ayaan Anwar , Yijie Yang , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH 0/6] Additional regulator support for the Qualcomm SGMII SerDes PHY Message-ID: References: <20251124-sgmiieth_serdes_regulator-v1-0-73ae8f9cbe2a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI2MDA0NyBTYWx0ZWRfXyWedvzWeV7fA Kih7JR6sHG2YaE/RDlYljwDaBOwCcPJdKlrIZu+S+q+yI7Md70l0SjY89x7oEcgNqP54EMQ1QoK CG92J0PUGRfz7JDZoaTA6T9/Ok37h2A= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI2MDA0NyBTYWx0ZWRfX32nJt8ErsP7h XLlYtlkCjDe2Dt2Kduu/EnhKoMJDPa1+I1m2UNmSaGWQcYmBbRUlr91i+l4tbqvpuyiC3gGFEi/ lD3IPEifyLl+k4A8RW9c1CLNj6u6XMOG0kV5qF7Rq51oUSVuCw84Ua+dRGpKcO7MEtVI0/BfeX8 WfQDf7EuMmY9tEU3jprc85fOw/9JFjKRPPwnmOzM2dSdUwqSueMFmKoxD3xfA4C6Kgo90TmkRGQ YEtok0SsGXPRS4+4Bg1RlNrJeEIfzjL2hiJgAShTm2iS1tkFBRtmdyy3QJRGU0Qb0AJlLmGnkj9 DtH4PP/SWAibQLqOpJ7HsDf8YvqWSu2nUCeflUZvgZmABZeXuhQiQkPPgDZcxnWXEeCijxWoZ9G rEiR5nAE+xvK1VfKHSiO8SETLNeLIOYa/wThR+7VZ0Qyo7k8X+5If4umW1gdczM4kHlLJOHpynk 8Ea7FALRMBqdDBE8okA== X-Authority-Analysis: v=2.4 cv=O4oJeh9W c=1 sm=1 tr=0 ts=6a3e18a0 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=evnvvmh2EKmFMqWf2KwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: QIudzVNGcwiWEzBTt3jr2wxiGvhGWDfZ X-Proofpoint-GUID: QIudzVNGcwiWEzBTt3jr2wxiGvhGWDfZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-26_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606260047 On Mon, Jun 22, 2026 at 04:08:55PM +0200, Loic Poulain wrote: > Hi, > > On Mon, Nov 24, 2025 at 10:26 AM Mohd Ayaan Anwar > wrote: > > > > This patch series addresses a SerDes power-up failure observed on the > > QCS8300 Ride board using the phy-qcom-sgmii-eth driver. The issue occurs > > because the SerDes PHY requires both L5A and L4A regulators to be > > enabled during initialization. If either one of them is disabled, the > > status register does not reset, and the Ethernet interface fails to come > > up due to a timeout: > > > > [ 77.105651] qcom-dwmac-sgmii-phy 8909000.phy: QSERDES_COM_C_READY_STATUS timed-out > > [ 77.113447] qcom-ethqos 23040000.ethernet eth0: __stmmac_open: Serdes powerup failed > > > > Presumably, the issue is not seen on all users of this PHY because both > > regulators are often shared with other peripherals. However, the power > > rail schematics for boards using this SerDes PHY show that it is > > supplied by both L5A (1.2V) and L4A (0.9V) regulators. > > > > This series has been tested on the QCS8300 Ride board, and the reported > > issue was resolved. All Monaco and Lemans derivative boards require this > > new configuration as they use the same SerDes PHY. > > > > Signed-off-by: Mohd Ayaan Anwar > > This appears to be a real issue, but I haven’t seen a new version of > the series or any response to the feedback so far. Could you please > follow up on this? > I will shortly send out a v2. I got access to more details about the hardware, and it has two dedicated regulators which need to be enabled. The same requirements are there on all Lemans/Monaco-based boards. Ayaan