From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ADF63C09F1 for ; Wed, 17 Jun 2026 09:38:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781689120; cv=none; b=PYjhNuc16am6+ya+opPJVP8G8eQ1uZY077H+KUnqrvMBJmPu3a5omA8Tbz7uKf708kkdoYY6+ncrmyUeC8peRxL/DdrUGnH5IG5hQ2c51dS7zkXq4SYPukIq03pZ8L1XGQzJlBY2ArIyAzU0MlRVcd9PTUGMMNuVE8tSaWA5r7Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781689120; c=relaxed/simple; bh=rgm36y2OpGnpfZDyJq45v+u5S54koPvVYpOixi6Jo6E=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CYsgNHrA9rrqL/M56EvQ2oNfrqeUNKtCwZufNlxa4g/K5d7sF2IzoK6DkWegIzm4aMlS5qtXAtFKJSQRFr70qL4UrfjnUbpSizEFteP0rWHY2mMsSMXXgGURTy8Vp0+JmZVP4PW0mK54mDbNgyRB7JhT4D6PHwJ8kvUSRnO5v1U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=XaPtupS/; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="XaPtupS/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=date:from:to:cc:subject:message-id :references:mime-version:content-type:in-reply-to; s=k1; bh=rgm3 6y2OpGnpfZDyJq45v+u5S54koPvVYpOixi6Jo6E=; b=XaPtupS/JnmjRKBJ4YPp 0DigDPNogMfztF9OWk+MC+NvlOQB/SJWWIdeGMxxyt1n7b0tuu9g9nmSqmlbgmuO VErKW7IZ8TQXGF+jI3kqVpN9vSKEWRkTFhGNl6IwHtYXoufSPNq3P1tkCxn5yLju w1wtD5mdq7A+OoUg+eHwDM4eyx51jlDosw9198ziES7uqKuspNXH+3vuxdQM6iUL XQ7VuoJxe/k6vVCGWZ7KajoslCiBn0x7l6vCxOEtsHCdzK84IsuNPhlWFhuZxG4M IAcOp+JdkuaMFRHD4xoIs5UiwY7O0eIQKd8GfjTDlsdqyUS6Eupll80dR67Bbzvc AQ== Received: (qmail 106160 invoked from network); 17 Jun 2026 11:38:36 +0200 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 17 Jun 2026 11:38:36 +0200 X-UD-Smtp-Session: l3s3148p1@2HrX0m9UiKQujnvI Date: Wed, 17 Jun 2026 11:38:35 +0200 From: Wolfram Sang To: Prabhakar Cc: Miquel Raynal , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Subject: Re: [PATCH 01/12] dt-bindings: rtc: renesas,rzn1-rtc: Add RZ/T2H and RZ/N2H support Message-ID: References: <20260615154805.1619693-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260615154805.1619693-2-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="9KewOfIgVqcuK8jH" Content-Disposition: inline In-Reply-To: <20260615154805.1619693-2-prabhakar.mahadev-lad.rj@bp.renesas.com> --9KewOfIgVqcuK8jH Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 15, 2026 at 04:47:54PM +0100, Prabhakar wrote: > From: Lad Prabhakar >=20 > Add compatible strings for the RTC block found on the Renesas RZ/T2H > (R9A09G077) and RZ/N2H (R9A09G087) SoCs. >=20 > These SoCs integrate a closely related variant of the RZ/N1 RTC IP. > Unlike RZ/N1, they do not implement the RTCA0SUBU and RTCA0TCR > registers. This is not a limitation for Linux support, as these > registers are not used when the RTC operates in "scmp" clock mode, which > is required on RZ/T2H and RZ/N2H due to their 195.3 kHz input clock. >=20 > The RZ/T2H RTC variant also supports a 1Hz output signal on the > RTCAT1HZ pin, controlled by the RTCA0CTL1[RTCA01HZE] bit. This bit is > marked as reserved in the RZ/N1 hardware manual. >=20 > Update the binding schema to require the additional clock inputs used by > these SoCs. >=20 > Signed-off-by: Lad Prabhakar Sashiko is wrong here because a) TCR is the "Test Register" b) TCR is not even present on RZ/N1D. Cover-letter misses that, too. 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