Re: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC

[Wolfram Sang <wsa+renesas@sang-engineering.com>]

[-- Attachment #1: Type: text/plain, Size: 1205 bytes --]

Hi Biju,

On Wed, Jun 03, 2026 at 07:57:01AM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
> controller is similar to RZ/G2L but has five clocks (core, clkh,
> cd, aclk, aclkm) and three resets (rst, axim, axis), so update the
> clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
> It has an internal divider for all modes except HS400, and a 2048-bit
> divider compared to 512 on others.
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

I know you work on v18 already, but some high level remarks already.

> +              - description: ACLK/IACLKS, SDHI channel bus clock.
> +              - description: IACLKM, SDHI channel bus clock m.

What does 's' and 'm' stand for? Is it mentioned in the docs? Would be
nice to have here as well, if so.

> +          resets:
> +            items:
> +              - description: rst, Core reset.
> +              - description: axim, SDHI axi bus reset m.
> +              - description: axis, SDHI axi bus reset s.

Ditto.

Happy hacking,

   Wolfram


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]