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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c7c52d669sm42698612eec.11.2026.06.28.22.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2026 22:18:54 -0700 (PDT) Date: Sun, 28 Jun 2026 22:18:52 -0700 From: Qiang Yu To: Konrad Dybcio Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros Message-ID: References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> <20260518-link_mode_0519-v4-2-269cd73cc5d1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA0MyBTYWx0ZWRfX7LrFrJJv3MEP v6g68h7AHXOtioFIr9aEp+BbjF1aJE5gJgR+Kgsa1cq1ntyE9SAHK1Eyc5CvwbeJ0AuwrkM2/BW Yu1h0oZ2jGJTZn/VQzqZbyE18abU2bs= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA0MyBTYWx0ZWRfX8n6m5C9tI2ya deeaDJ/y1ezU2wZjOjcKLbVMeoU3FbwVFeTmj+5pYNGyPMuPg0QcxMOwfzZ9EJo7sP5uZccLYri v2E+ce5BjEPGdHKDCnMcBQouKG3h23JdNWeiRX7sMMCGNiNyhGKf7Y8rwyfX8JnkJJWFP2C1tuF vZEXHoU13ZGJmyJONLUYB9wxlOX673b7rLxTW8zDwcYU6PjHL49V6P8t0/7yPCbhAxZRquifEgo Az/u3nwceHLowdP+1OZX8Zrkc5sHHAFi28zp79tY8WJries/Wa24wIIfO77Avc5+dxzYn7Y7wQo RTcM0bPNvMAVeYxMRU+sTCfCGJmcz2/Pxq/QQ4I63fVIrP25zbU6o7x8RBO9ok1r8HEej33UCJ7 fL4pY/aDSljmQLZEizm50TaZV1hBtsdjnV3gZvVyEkRmU7gjAycSnF8JXBvYr4URhXIOqK4Y33p G5lVp0TS3Kp6FsWSOfA== X-Proofpoint-GUID: LBZDU9RtwOaKxt9ivl6XPKXwbNa54Bde X-Proofpoint-ORIG-GUID: LBZDU9RtwOaKxt9ivl6XPKXwbNa54Bde X-Authority-Analysis: v=2.4 cv=DY8nbPtW c=1 sm=1 tr=0 ts=6a420040 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=vrcMDjKIvnehLc830DYA:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290043 On Tue, Jun 16, 2026 at 04:07:27PM +0200, Konrad Dybcio wrote: > On 5/19/26 7:47 AM, Qiang Yu wrote: > > Add two sets of constants to phy-qcom-qmp.h to support upcoming multiple > > link mode QMP PHY: > > > > - QMP_PHY_SELECTOR_0 / QMP_PHY_SELECTOR_1: generic logical PHY index > > values for QMP providers that expose multiple PHY instances under a > > single DT node (i.e. #phy-cells = <1>). > > > > - QMP_PCIE_GLYMUR_MODE_X8 / QMP_PCIE_GLYMUR_MODE_X4X4: link-mode > > values for the Glymur Gen5x8 PCIe PHY "qcom,link-mode" syscon property, > > selecting between the x8 single-PHY and x4+x4 dual-PHY topologies. > > > > Signed-off-by: Qiang Yu > > --- > > include/dt-bindings/phy/phy-qcom-qmp.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h > > index 6b43ea9e0051..befa76f8392f 100644 > > --- a/include/dt-bindings/phy/phy-qcom-qmp.h > > +++ b/include/dt-bindings/phy/phy-qcom-qmp.h > > @@ -21,4 +21,12 @@ > > #define QMP_PCIE_PIPE_CLK 0 > > #define QMP_PCIE_PHY_AUX_CLK 1 > > > > +/* Generic QMP logical PHY selectors */ > > +#define QMP_PHY_SELECTOR_0 0 > > +#define QMP_PHY_SELECTOR_1 1 > > Is this for the second phy cell? FWIW I think it's fine to use raw > numbers as they're just indices (i.e. "nth bifurcated phy") anyway I can't use lane numbers. In x4+x4 case, I need to tell phy the first 4 lanes or second 4 lanes are required. - Qiang Yu