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From: Drew Fustini <fustini@kernel.org>
To: yunhui cui <cuiyunhui@bytedance.com>
Cc: "Adrien Ricciardi" <aricciardi@baylibre.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Babu Moger" <babu.moger@amd.com>,
	"Ben Horgan" <ben.horgan@arm.com>,
	"Borislav Petkov" <bp@alien8.de>,
	"Chen Pei" <cp0613@linux.alibaba.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	"Dave Martin" <Dave.Martin@arm.com>,
	"Fenghua Yu" <fenghuay@nvidia.com>,
	"Gong Shuai" <gong.shuai@sanechips.com.cn>,
	"Gong Shuai" <gsh517@gmail.com>,
	guo.wenjia23@zte.com.cn, "James Morse" <james.morse@arm.com>,
	"Kornel Dulęba" <mindal@semihalf.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	liu.qingtao2@zte.com.cn,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <pjw@kernel.org>,
	"Peter Newman" <peternewman@google.com>,
	"Radim Krčmář" <rkrcmar@ventanamicro.com>,
	"Reinette Chatre" <reinette.chatre@intel.com>,
	"Rob Herring" <robh@kernel.org>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
	"Tony Luck" <tony.luck@intel.com>,
	"Vasudevan Srinivasan" <vasu@rivosinc.com>,
	"Ved Shanbhogue" <ved@rivosinc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	x86@kernel.org, devicetree@vger.kernel.org,
	linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org
Subject: Re: [External] [PATCH v5 4/8] riscv_cbqri: Add capacity controller probe and allocation device ops
Date: Mon, 20 Jul 2026 10:12:47 -0700	[thread overview]
Message-ID: <al5XD5UbluV_NyE3@thelio> (raw)
In-Reply-To: <CAEEQ3w=9JKswTz9BcxXRvLh-kyN_Rdu3=YUR5Rey2J9UNyd0AA@mail.gmail.com>

On Mon, Jul 20, 2026 at 08:12:28PM +0800, yunhui cui wrote:
> Hi Drew,
> 
> On Wed, Jul 15, 2026 at 8:24 AM Drew Fustini <fustini@kernel.org> wrote:
> >
> > Add support for the RISC-V CBQRI capacity controller. A platform driver
> > passes a cbqri_controller_info descriptor together with the cache level
> > to riscv_cbqri_register_cc_dt(), which probes the controller and adds it
> > to the controller list.
> >
> > Assisted-by: Claude:claude-opus-4-8
> > Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > ---
> >  MAINTAINERS                      |   3 +
> >  drivers/resctrl/Kconfig          |  13 +
> >  drivers/resctrl/Makefile         |   3 +
> >  drivers/resctrl/cbqri_devices.c  | 563 +++++++++++++++++++++++++++++++++++++++
> >  drivers/resctrl/cbqri_internal.h | 122 +++++++++
> >  include/linux/riscv_cbqri.h      |  45 ++++
> >  6 files changed, 749 insertions(+)
[..]
> > +static int cbqri_probe_cc(struct cbqri_controller *ctrl)
> > +{
> > +       int err, status;
> > +       int ver_major, ver_minor;
> > +       u64 reg;
> > +
> > +       reg = cbqri_readq(ctrl->base + CBQRI_CC_CAPABILITIES_OFF);
> > +       if (reg == 0)
> > +               return -ENODEV;
> > +
> > +       ver_minor = FIELD_GET(CBQRI_CC_CAPABILITIES_VER_MINOR_MASK, reg);
> > +       ver_major = FIELD_GET(CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK, reg);
> > +       ctrl->cc.ncblks = FIELD_GET(CBQRI_CC_CAPABILITIES_NCBLKS_MASK, reg);
> > +
> > +       pr_debug("version=%d.%d ncblks=%d cache_level=%d\n",
> > +                ver_major, ver_minor,
> > +                ctrl->cc.ncblks, ctrl->cache.cache_level);
> > +
> > +       /*
> > +        * NCBLKS == 0 would divide-by-zero in the schemata math while
> > +        * ctrl->lock is held.
> > +        */
> > +       if (!ctrl->cc.ncblks) {
> > +               pr_warn("CC at %pa has 0 capacity blocks, skipping\n",
> > +                       &ctrl->addr);
> > +               return -ENODEV;
> > +       }
> > +
> > +       if (ctrl->cc.ncblks > 32) {
> > +               pr_warn("CC at %pa has ncblks=%u > 32 (resctrl CBM is u32), skipping\n",
> > +                       &ctrl->addr, ctrl->cc.ncblks);
> > +               return -ENODEV;
> > +       }
> 
> Could you add a short comment here, like MPAM does, to note that the
> NCBLKS <= 32 limit comes from resctrl using u32 bitmap configs?

Sure, I will add a comment that the limit comes from resctrl
representing the CBM as a u32.

Thanks,
Drew

  reply	other threads:[~2026-07-20 17:12 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-15  0:23 [PATCH v5 0/8] riscv: Add Ssqosid and initial CBQRI resctrl support Drew Fustini
2026-07-15  0:23 ` [PATCH v5 1/8] dt-bindings: riscv: Add Ssqosid extension description Drew Fustini
2026-07-15  0:23 ` [PATCH v5 2/8] riscv: Detect the Ssqosid extension Drew Fustini
2026-07-15  0:23 ` [PATCH v5 3/8] riscv: Add support for srmcfg CSR from " Drew Fustini
2026-07-15  0:23 ` [PATCH v5 4/8] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-07-20  9:56   ` [External] " yunhui cui
2026-07-20 17:10     ` Drew Fustini
2026-07-20 12:12   ` yunhui cui
2026-07-20 17:12     ` Drew Fustini [this message]
2026-07-15  0:23 ` [PATCH v5 5/8] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-07-15  0:23 ` [PATCH v5 6/8] riscv: Enable resctrl filesystem for Ssqosid Drew Fustini
2026-07-15  0:23 ` [PATCH v5 7/8] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-07-15  0:23 ` [PATCH v5 8/8] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini

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