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Mon, 13 Jul 2026 06:32:02 -0700 (PDT) Date: Mon, 13 Jul 2026 15:32:00 +0200 From: Stefano Radaelli To: Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, pierluigi.p@variscite.com, matthias.p@variscite.com, Stefano Radaelli , Nishanth Menon , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration Message-ID: References: <4d1ba0d1b9bd4957224213cf17dca93392788e03.1782680023.git.stefano.r@variscite.com> <531d7396-c581-4b5d-8008-db5e9ee5e7d6@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <531d7396-c581-4b5d-8008-db5e9ee5e7d6@ti.com> On Mon, Jul 13, 2026 at 04:02:34PM +0530, Vignesh Raghavendra wrote: > > > > &cpsw3g_mdio { > > @@ -159,9 +169,9 @@ &cpsw3g_mdio { > > cpsw3g_phy0: ethernet-phy@4 { > > compatible = "ethernet-phy-id0283.bc30"; > > reg = <4>; > > - reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; > > - reset-assert-us = <10000>; > > - reset-deassert-us = <100000>; > > So are the reset delays no longer required? Or they taken care of > somewhere else? > > > + bootph-all; > > + enet-phy-lane-no-swap; > > + vdd-supply = <®_eth_phy_vdd>; > > }; > > }; > > > > -- > Regards > Vignesh > https://ti.com/opensource > Hi Vignesh, No, because this GPIO actually is not used as a PHY reset. After reviewing the hardware, it turned out that this signal is a board-level enable signal required for the PHY to operate, rather than a reset line. The previous reset-assert-us and reset-deassert-us values were associated with the incorrect modelling of this GPIO as a reset, and are not longer needed. Thank you! Best Regards, Stefano