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From: Brian Masney <bmasney@redhat.com>
To: Simon Glass <sjg@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
	Fabio Estevam <festevam@nabladev.com>,
	devicetree@vger.kernel.org, Jonas Karlman <jonas@kwiboo.se>,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	Jeffy Chen <jeffy.chen@rock-chips.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, huang lin <hl@rock-chips.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/6] clk: rockchip: Add clock controller for the RV1106
Date: Tue, 21 Jul 2026 19:20:30 -0400	[thread overview]
Message-ID: <al_-vioCVeQxVo-f@redhat.com> (raw)
In-Reply-To: <20260714193656.2196447-3-sjg@chromium.org>

Hi Simon,

On Tue, Jul 14, 2026 at 01:36:39PM -0600, Simon Glass wrote:
> +static void __init rv1106_clk_init(struct device_node *np)
> +{
> +	struct rockchip_clk_provider *ctx;
> +	unsigned long clk_nr;
> +	void __iomem *reg_base;
> +	int ret;
> +
> +	clk_nr = rockchip_clk_find_max_clk_id(rv1106_clk_branches,
> +					      ARRAY_SIZE(rv1106_clk_branches)) + 1;
> +	clk_nr = max(clk_nr,
> +		     rockchip_clk_find_max_clk_id(rv1106_grf_clk_branches,
> +					ARRAY_SIZE(rv1106_grf_clk_branches)) + 1);
> +	reg_base = of_iomap(np, 0);
> +	if (!reg_base) {
> +		pr_err("%s: could not map cru region\n", __func__);
> +		return;
> +	}
> +
> +	ctx = rockchip_clk_init(np, reg_base, clk_nr);
> +	if (IS_ERR(ctx)) {
> +		pr_err("%s: rockchip clk init failed\n", __func__);
> +		iounmap(reg_base);
> +		return;
> +	}
> +
> +	rv1106_pvtpll_init(ctx);
> +
> +	rockchip_clk_register_plls(ctx, rv1106_pll_clks,
> +				   ARRAY_SIZE(rv1106_pll_clks),
> +				   RV1106_GRF_SOC_STATUS0);
> +
> +	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
> +				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
> +				     &rv1106_cpuclk_data, rv1106_cpuclk_rates,
> +				     ARRAY_SIZE(rv1106_cpuclk_rates));
> +
> +	rockchip_clk_register_branches(ctx, rv1106_clk_branches,
> +				       ARRAY_SIZE(rv1106_clk_branches));
> +
> +	/*
> +	 * The MMC drive and sample phase clocks have their control
> +	 * registers in the GRF region, so they can only be provided when
> +	 * the rockchip,grf property points at a valid syscon.
> +	 */
> +	if (!IS_ERR(ctx->grf)) {
> +		ret = rockchip_clk_add_grf(ctx, ctx->grf, grf_type_sys);
> +		if (ret)
> +			pr_err("%s: failed to add grf: %d\n", __func__, ret);
> +		else
> +			rockchip_clk_register_branches(ctx,
> +					rv1106_grf_clk_branches,
> +					ARRAY_SIZE(rv1106_grf_clk_branches));
> +	}
> +
> +	rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
> +
> +	rockchip_clk_of_add_provider(np, ctx);
> +}
> +
> +CLK_OF_DECLARE(rv1106_cru, "rockchip,rv1106-cru", rv1106_clk_init);

Can this be registered as a platform driver similar to
drivers/clk/rockchip/clk-rk3528.c ?

Brian


  parent reply	other threads:[~2026-07-21 23:20 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-14 19:36 [PATCH v2 0/6] Add support for the Rockchip RV1106 and RV1103 Simon Glass
2026-07-14 19:36 ` [PATCH v2 1/6] dt-bindings: clock: rockchip: Add RV1106 CRU support Simon Glass
2026-07-14 19:54   ` sashiko-bot
2026-07-22 17:16   ` Rob Herring (Arm)
2026-07-14 19:36 ` [PATCH v2 2/6] clk: rockchip: Add clock controller for the RV1106 Simon Glass
2026-07-14 20:09   ` sashiko-bot
2026-07-21 23:20   ` Brian Masney [this message]
2026-07-14 19:36 ` [PATCH v2 3/6] dt-bindings: soc: rockchip: grf: Add RV1106 compatibles Simon Glass
2026-07-21  8:16   ` Krzysztof Kozlowski
2026-07-21 12:30     ` Heiko Stübner
2026-07-14 19:36 ` [PATCH v2 4/6] ARM: dts: rockchip: Add support for RV1106 and RV1103 Simon Glass
2026-07-14 20:42   ` sashiko-bot
2026-07-14 19:36 ` [PATCH v2 5/6] dt-bindings: arm: rockchip: Add Luckfox Pico Mini B Simon Glass
2026-07-14 20:50   ` sashiko-bot
2026-07-14 19:36 ` [PATCH v2 6/6] ARM: dts: " Simon Glass

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