Re: [PATCH 2/9] arm64: dts: imx8ulp: Add I3C2 controller node

[Frank Li <Frank.li@oss.nxp.com>]

On Wed, Jul 15, 2026 at 12:42:07PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The device tree assigns a dummy clock for 'slow_clk', contradicting the commit message which states it is configured to use the 24 MHz PCC3-gated clock.
> --
>
> --- Patch [2]: [PATCH 2/9] arm64: dts: imx8ulp: Add I3C2 controller node ---
> commit 56028cef3837517bbf3f1ac9d58c6983788955ee
> Author: Peng Fan <peng.fan@nxp.com>
>
> arm64: dts: imx8ulp: Add I3C2 controller node
>
> This commit adds the I3C2 node to the imx8ulp device tree using the
> Silvaco I3C master IP. It also configures the controller's interrupts
> and clock sources.
>
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > index 5438958176985..c82c3388cbe79 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> [ ... ]
> > @@ -361,6 +361,22 @@ tpm5: tpm@29340000 {
> [ ... ]
> > +			i3c2: i3c@29360000 {
> > +				compatible = "silvaco,i3c-master-v1";
> > +				reg = <0x29360000 0x10000>;
> > +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > +				#address-cells = <3>;
> > +				#size-cells = <0>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_I3C2>,
> > +					 <&pcc3 IMX8ULP_CLK_I3C2>,
> > +					 <&cgc1 IMX8ULP_CLK_DUMMY>;
> > +				clock-names = "pclk", "fast_clk", "slow_clk";
>
> [Severity: Medium]
> Does this clock assignment match the intention described in the commit message?
>
> The commit message states that the PCC3-gated clock is configured "for pclk,
> fast_clk and slow_clk". However, the device tree node assigns the dummy clock
> (&cgc1 IMX8ULP_CLK_DUMMY) for slow_clk instead.
>
> Should slow_clk be using &pcc3 IMX8ULP_CLK_I3C2 as described, or should the
> commit message be updated to reflect the use of the dummy clock?

Make sense, update commit messge or set slow_clk to &pcc3 IMX8ULP_CLK_I3C2

Frank
>
> > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>;
> > +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
> > +				assigned-clock-rates = <24000000>;
> > +				status = "disabled";
> > +			};
> [ ... ]
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260715-imx8ulp-dts-v1-0-19651358b599@nxp.com?part=2