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Received: from authenticated user by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wkTfj-00000003GSb-2MgD; Thu, 16 Jul 2026 23:31:11 +0200 Date: Thu, 16 Jul 2026 23:31:10 +0200 From: Aurelien Jarno To: Inochi Amaoto Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: Re: [PATCH 1/2] riscv: dts: spacemit: k3: add USB controller and USB phy support Message-ID: Mail-Followup-To: Inochi Amaoto , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li References: <20260709040415.977784-1-inochiama@gmail.com> <20260709040415.977784-2-inochiama@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260709040415.977784-2-inochiama@gmail.com> User-Agent: Mutt/2.2.13 (2024-03-09) On 2026-07-09 12:04, Inochi Amaoto wrote: > Add all USB device node to the Spacemit K3. > > Signed-off-by: Inochi Amaoto > --- > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ > arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ > 2 files changed, 55 insertions(+) > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > index b89c1521e664..2a6d35a64d5c 100644 > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > @@ -182,6 +182,11 @@ dldo7: dldo7 { > }; > }; > > +&combophy { > + spacemit,apmu = <&syscon_apmu 0x11>; > + status = "okay"; > +}; > + > ð0 { > pinctrl-names = "default"; > pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; > @@ -221,3 +226,11 @@ hub@1 { > &usb2_phy { > status = "okay"; > }; > + > +&usb3d_u2phy { > + status = "okay"; > +}; > + > +&usb3d { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > index 19fc9b49668e..82c9e2da82e9 100644 > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > @@ -7,6 +7,7 @@ > #include > #include > #include > +#include > > /dts-v1/; > > @@ -438,6 +439,47 @@ soc: soc { > dma-noncoherent; > ranges; > > + usb3d: usb@81a00000 { > + compatible = "spacemit,k3-dwc3"; > + reg = <0x0 0x81a00000 0x0 0x10000>; > + interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&saplic>; > + clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; > + clock-names = "usbdrd30"; > + resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, > + <&syscon_apmu RESET_APMU_USB3_D_VCC>, > + <&syscon_apmu RESET_APMU_USB3_D_PHY>; > + reset-names = "ahb", "vcc", "phy"; > + phys = <&usb3d_u2phy>, > + <&combophy 4 PHY_TYPE_USB3>; > + phy-names = "usb2-phy", "usb3-phy"; > + phy_type = "utmi"; > + snps,dis_enblslpm_quirk; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + snps,dis-del-phy-power-chg-quirk; > + snps,dis-tx-ipgap-linecheck-quirk; > + snps,parkmode-disable-ss-quirk; > + dr_mode = "host"; > + status = "disabled"; > + }; > + > + usb3d_u2phy: phy@81b00000 { > + compatible = "spacemit,k3-usb2-phy"; > + reg = <0x0 0x81b00000 0x0 0x200>; > + clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; This should be CLK_APMU_USB3_PORTD_BUS. I am also not sure you want to declare the USB3 PHY in k3.dtsi. I think it should be defined at the board level, as other boards than the k3 Pico ITX might decide to keep this controller as USB 2 only and use the combo PHY for PCIe. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net