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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31429fe1014sm853004eec.7.2026.07.16.18.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 18:20:33 -0700 (PDT) Date: Thu, 16 Jul 2026 18:20:32 -0700 From: Peter Chen To: Thinh Nguyen Cc: Krishna Kurapati , Krzysztof Kozlowski , Dmitry Baryshkov , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , "linux-arm-msm@vger.kernel.org" , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v4 1/2] dt-bindings: qcom,snps-dwc3: Add property indicating presence of eUSB2 phy Message-ID: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Authority-Analysis: v=2.4 cv=IMIyzAvG c=1 sm=1 tr=0 ts=6a598363 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=gzHRHKxzVZXRfne5p3sA:9 a=CjuIK1q_8ugA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDAxMCBTYWx0ZWRfX7oF/tVg1PP+k opIH7gRUn6bdvGReWSzT4NUEh7mBStPB3EVZRYjAX7lUzFV+5mpMdamPxyVxY92Zt5atl0uqlff Lro6tCYdNICJxaduQKsuJQYlvwEOMaEzE6LGPimPgUryXnhP3BH9G5KLRHAKhxAohDxhIMB0QNk T4j//FbLBAO1trj+NYERb9XSMvrbmismrrd6my9mKZhEi3hrK3nX4UOE9KelmI9NSYp0BQDCZVg /LWAPgFJy5gqbKvvLNig/Inh33Ia7S0xqVatK+Vvm6JxlcwpMKS4kArAswsNjqPg38+0VOZc8U4 evmTmof029za/KBIRUCXzev+rjJhCKqQopsktCEw2E11lgbRgdeoi1DIop5Q5fXEpd0RBzoTPrv 9e/kPi6nEDpq2xkxeAtfu8rlna3i1dElWrMqGGWfi9vBqu3aYzYw2prMFdTLbzc3SWI+jqSlTQ2 VQbbUeKt5htJ5V1nonQ== X-Proofpoint-GUID: ULhQRqmiR2_4La3MGFpWf0UVCmJlmWBR X-Proofpoint-ORIG-GUID: ULhQRqmiR2_4La3MGFpWf0UVCmJlmWBR X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDAxMCBTYWx0ZWRfXwDMQAgzouAS6 Kn7aJpLP5k/s0ehdtvtjorVb3P3vtfWFfbc+nrTu+q8M/dfK0m0vDSttmI5kjngk1uRRlNDubk2 k1omS5xhzhkKwJRP3/TlBRV1zQ4YJiw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_08,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170010 On 26-07-17 00:06:37, Thinh Nguyen wrote: > > > > I have seen fewer platforms use "phy_type" at dts for arm64, dwc3 > > core uses it only for special cases and the code was added for > > ten years ago. For the default situation, we may not need to > > change DWC3_GUSB2PHYCFG_EUSB2OPMODE value for UTMI+, Thinh, is it > > correct? > > > > The GUSB2PHYCFG.eUSB2OPMODE is only relevant for host mode and mainly > for electrical compliance. Usually by default, the CoreConsultant > setting should have this set correctly. So not explicitly setting it > should be functionally fine (IIRC). > > That said, this is separate from the GUSB2PHYCFG.PHYIF, which the core > uses dwc->hsphy_mode to indicate whether the UTMI interface is 8-bit or > 16-bit. > Why only rockchip uses this "phy_type" property, why other SoC vendors no this requirement for UTMI width setting? -- Thanks, Peter Chen