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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3142a1de301sm1702185eec.24.2026.07.16.20.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 20:42:24 -0700 (PDT) Date: Thu, 16 Jul 2026 20:42:22 -0700 From: Peter Chen To: Thinh Nguyen Cc: Krishna Kurapati , Krzysztof Kozlowski , Dmitry Baryshkov , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , "linux-arm-msm@vger.kernel.org" , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v4 1/2] dt-bindings: qcom,snps-dwc3: Add property indicating presence of eUSB2 phy Message-ID: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDAzMSBTYWx0ZWRfXwmc/073AzO1E QVILJR91/z5x1tgkqoIyuIEjtmFTLjvtwLfiIsWTPXaQZdDOOMP+HGeRKKOJNCRLib1hBGJVfhl fw14bZxQPvcyurDFHKIxiAx0NDWjTN2mp6iO5Fcxmof1s5ooiEcaetn6cls1CK6tav0sgy4Kgb3 kR7hv9KOrfMMyopZ2o5H4yySVTaf3MiPOQ2IfGsilFUZCgl6RGDoqfWXMMacT5CUHOLtYtdrfm5 eo2PkvqyCGy8l/ynLFwa9se+upAKA3X8mfgs6RkpAWeMUO/1tW3rFJw6kmzkDaLKl+kTzM6/WHq /FzjL4FU29oXdOyo3/VfvIIzP3lW0hvwUyMBbZ2WwYuknNf62ZNp2FmyBxImKlapWUczRO9JNax BIljtG06DxXlF4SaDbWg5ogkRLT6RtT1aWETDg2llaijg3V4yCWm6kss+T2oeiRCFAYqRMiLYw7 uBvf7D8C0YJG9wCkJ0Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDAzMSBTYWx0ZWRfX/3SsWud/sI9z wjVqcbGipDJEt5fWKAyrcD0N3CdU7BOc+JgI8KE0vEUezV5QjubdUKn3NLXQEjFiOqz1fRuYmqX 5uWAdGB27fg1ArrblPFooSbYKQf+eO8= X-Authority-Analysis: v=2.4 cv=DYMnbPtW c=1 sm=1 tr=0 ts=6a59a4a2 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=zDMlSImzIToMmpLGiZwA:9 a=CjuIK1q_8ugA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: 26zWZ3RrogdX78Z7WFXb12OYukQbFo-g X-Proofpoint-ORIG-GUID: 26zWZ3RrogdX78Z7WFXb12OYukQbFo-g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-17_01,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170031 On 26-07-17 01:56:59, Thinh Nguyen wrote: > On Thu, Jul 16, 2026, Peter Chen wrote: > > On 26-07-17 00:06:37, Thinh Nguyen wrote: > > > > > > > > I have seen fewer platforms use "phy_type" at dts for arm64, dwc3 > > > > core uses it only for special cases and the code was added for > > > > ten years ago. For the default situation, we may not need to > > > > change DWC3_GUSB2PHYCFG_EUSB2OPMODE value for UTMI+, Thinh, is it > > > > correct? > > > > > > > > > > The GUSB2PHYCFG.eUSB2OPMODE is only relevant for host mode and mainly > > > for electrical compliance. Usually by default, the CoreConsultant > > > setting should have this set correctly. So not explicitly setting it > > > should be functionally fine (IIRC). > > > > > > That said, this is separate from the GUSB2PHYCFG.PHYIF, which the core > > > uses dwc->hsphy_mode to indicate whether the UTMI interface is 8-bit or > > > 16-bit. > > > > > > > Why only rockchip uses this "phy_type" property, why other SoC vendors > > no this requirement for UTMI width setting? > > > > Not just rockchip, some tegra and hikey also use it. Some old qcom dts > files also have it for ulpi. Tegra and old qcom platforms use chipidea, hikey uses dwc3. > > It is typically set when the coreConsultant default differs from what > the platform needs, so the driver can override it with the correct > setting. > > My point is that changing "phy_type" definition is more involved than it > looks. I'm open to alternatives. > I know your concern that in case the eUSB2 PHY SoC wants to change UTMI width, it can't do that. Are there controller register know it connects eUSB2 PHY? For the place to put "eusb2" for phy type, I still think enum usb_phy_interface at: include/linux/usb/phy.h is the most suitable place, would you have any alternatives? Another solution is using generic PHY API phy_get_mode, set fixed "eusb2" mode at eUSB2 PHY driver, but it depends on PHY driver doesn't have different settings for device and host mode. Other solution is compare the generic PHY compatible string at dwc3 qcom glue layer, it depends on eUSB2 PHY compatible string always contains "eusb2-phy" I prefer the solution that extend enum usb_phy_interface for eUSB2 PHY, it uses existed kernel structure and device tree binding. -- Thanks, Peter Chen