From: atull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
To: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Dinh Nguyen
<dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Grant Likely
<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org
Subject: Re: [PATCH 1/2] ARM: socfpga: Add driver for the L3 interconnect
Date: Wed, 29 Oct 2014 15:30:10 -0500 [thread overview]
Message-ID: <alpine.DEB.2.02.1410291521290.29374@atx-linux-37> (raw)
In-Reply-To: <1414582436-12772-1-git-send-email-s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
On Wed, 29 Oct 2014, Steffen Trumtrar wrote:
> The L3 interconnect provides Global Programmer View (GPV) registers for every
> AXI master and slave on the SoC.
> Although this is just a bunch of bits, syscon is not the right approach for
> this IP core.
> The L3 interconnect is configured with a lot of reserved "holes" in its memory
> space. Just mapping this with regmap, what syscon would do, would lead to the
> system completely hanging, if one of those areas would be touched.
> One example for when this might happen is the regmap registers dump in the
> debugfs.
>
> This driver specifies also the valid readable and writable ranges of the L3
> interconnect. Other drivers that want to access their GPV registers can do
> so with this driver via socfpga_l3nic_regmap_by_phandle.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> .../bindings/soc/socfpga/altr,l3-nic.txt | 15 ++
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/socfpga/Kconfig | 11 +
> drivers/soc/socfpga/Makefile | 1 +
> drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++
> include/soc/socfpga/gpv.h | 63 ++++++
> include/soc/socfpga/l3regs.h | 194 ++++++++++++++++++
> 8 files changed, 507 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt
> create mode 100644 drivers/soc/socfpga/Kconfig
> create mode 100644 drivers/soc/socfpga/Makefile
> create mode 100644 drivers/soc/socfpga/l3nic.c
> create mode 100644 include/soc/socfpga/gpv.h
> create mode 100644 include/soc/socfpga/l3regs.h
>
Hi Steffen,
This looks really nice and useful.
I tried it out with my bridge driver and at least with my superficial
testing it looked good.
> +
> +int socfpga_l3nic_regmap_by_phandle(struct device_node *np,
> + struct regmap **regmap,
> + const char *name)
> +{
This could return the regmap or ERR_PTR(-ENODEV) and just
have the np and name parameter, similar to
syscon_regmap_lookup_by_phandle.
Thanks!
Alan
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next prev parent reply other threads:[~2014-10-29 20:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-29 11:33 [PATCH 1/2] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar
[not found] ` <1414582436-12772-1-git-send-email-s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-10-29 11:33 ` [PATCH 2/2] ARM: dts: socfpga: Add l3nic node Steffen Trumtrar
2014-10-29 20:30 ` atull [this message]
2014-10-29 20:51 ` [PATCH 1/2] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar
[not found] ` <20141029205103.GF10262-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-10-29 21:12 ` Uwe Kleine-König
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