From: atull <atull@opensource.altera.com>
To: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: mark.rutland@arm.com, linux-doc@vger.kernel.org,
rubini@gnudd.com,
Pantelis Antoniou <pantelis.antoniou@konsulko.com>,
hpa@zytor.com, s.trumtrar@pengutronix.de,
devel@driverdev.osuosl.org, sameo@linux.intel.com,
Nicolas Pitre <nico@linaro.org>,
iws@ovro.caltech.edu, Michal Simek <michal.simek@xilinx.com>,
kyle.teske@ni.com, Grant Likely <grant.likely@linaro.org>,
David Brown <davidb@codeaurora.org>,
Linus Walleij <linus.walleij@linaro.org>,
cesarb@cesarb.net, devicetree@vger.kernel.org,
jason@lakedaemon.net, pawel.moll@arm.com,
ijc+devicetree@hellion.org.uk, Kumar Gala <galak@codeaurora.org>,
broonie@kernel.org, Philip Balister <philip@balister.org>,
Petr Cvek <petr.cvek@tul.cz>,
akpm@linux-foundation.org, Michal Simek <monstr@monstr.eu>,
Greg KH <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, balbi@ti.com, davem@davemloft.net,
robh+dt@kernel.org, Rob
Subject: Re: [PATCH v9 6/7] staging: add simple-fpga-bus
Date: Thu, 23 Jul 2015 22:42:05 -0500 [thread overview]
Message-ID: <alpine.DEB.2.02.1507232229580.5634@linuxheads99> (raw)
In-Reply-To: <20150723221510.GA16971@obsidianresearch.com>
On Thu, 23 Jul 2015, Jason Gunthorpe wrote:
> On Thu, Jul 23, 2015 at 02:55:52PM -0700, Moritz Fischer wrote:
> > Hi Alan,
> >
> > I saw that your socfpga driver doesn't support the partial reconfig
> > use case (not a big deal).
> > What I currently do for Zynq is if I'm doing a non-partial reconfig is
> > that I disable input
> > level shifters and assert *all* resets while reprogramming in my FPGA
> > manager .write_init() and .write_complete().
>
> I do this as well, but it is a bit more complex.. FPGA specific code
> has to run around and ensure all DMA is shut off, then we need to make
> sure no CPU issued AXI transactions can happen, then we can tear down
> the FPGA side.
>
> If the FPGA is torn down while an AXI op is inprogress things go
> sideways, we have to work to prevent that :)
>
> This happens almost for free, I use DT and the device model to
> disconnect the drivers. The drivers are careful to synchronously fence
> off in-progress DMA. Then drop the DT nodes associated with the
> FPGA, finally the actual FPGA cells can be reset.
Yes, the kernel gives us this almost for free. That's what I like
about using DT overlays to control FPGA programming.
>
> > In a partial reconfiguration situation, would I have separate
> > simple-fpga buses for each of the parts that I swap out, each with
> > it's own reset and bitfile attached?
>
> I'd think of partial reconfiguration as another nested FPGA. The
> resets and so forth could be attached to soft controllers in the
> unswappable part of the FPGA.
>
> DT nodes have to surround it in some way...
>
> Jason
>
Yes, in this way each PR chunk will need its own reset so it
won't wiggle busses and affect the rest of the system during PR.
I noticed that currently simple-fpga-bus.c holds an exclusive
ref of the fpga manager. This would keep a 2nd pr from being
able to access the same fpga manager, so I'll have to change
it so that simple-fpga-bus.c will put the ref before exiting
probe.
Alan
next prev parent reply other threads:[~2015-07-24 3:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-17 15:51 [PATCH v9 0/7] FPGA Manager Framework and Simple FPGA Bus atull
2015-07-17 15:51 ` [PATCH v9 1/7] staging: usage documentation for FPGA manager core atull
2015-07-23 6:38 ` Pavel Machek
2015-07-17 15:51 ` [PATCH v9 2/7] staging: usage documentation for simple fpga bus atull
2015-07-23 6:43 ` Pavel Machek
2015-07-17 15:51 ` [PATCH v9 3/7] staging: add bindings document " atull
2015-07-17 19:49 ` Steffen Trumtrar
2015-07-17 21:21 ` Jason Gunthorpe
2015-07-17 21:22 ` atull
2015-07-23 7:31 ` Steffen Trumtrar
2015-07-23 6:46 ` Pavel Machek
2015-07-17 15:51 ` [PATCH v9 4/7] staging: fpga manager: add sysfs interface document atull
2015-07-24 8:18 ` Pavel Machek
2015-07-24 12:39 ` atull
2015-07-24 12:43 ` Pavel Machek
2015-07-17 15:51 ` [PATCH v9 5/7] staging: fpga manager core atull
2015-07-17 17:27 ` Randy Dunlap
2015-07-17 18:25 ` atull
2015-07-22 21:47 ` Moritz Fischer
2015-07-23 16:28 ` atull
2015-07-17 15:51 ` [PATCH v9 6/7] staging: add simple-fpga-bus atull
2015-07-23 21:55 ` Moritz Fischer
2015-07-23 22:15 ` Jason Gunthorpe
2015-07-24 3:42 ` atull [this message]
2015-07-17 15:51 ` [PATCH v9 7/7] staging: fpga manager: add driver for socfpga fpga manager atull
2015-07-17 21:06 ` Moritz Fischer
2015-07-17 21:42 ` atull
2015-07-17 17:25 ` [PATCH v9 0/7] FPGA Manager Framework and Simple FPGA Bus Jason Gunthorpe
2015-07-17 18:09 ` atull
2015-07-22 20:32 ` atull
2015-07-22 21:11 ` Jason Gunthorpe
2015-07-22 21:39 ` atull
2015-07-23 4:12 ` Greg KH
2015-07-23 16:37 ` atull
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