From: Thomas Gleixner <tglx@linutronix.de>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Cernekee <cernekee@gmail.com>,
f.fainelli@gmail.com, jason@lakedaemon.net, ralf@linux-mips.org,
lethal@linux-sh.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, mbizon@freebox.fr, jogo@openwrt.org,
linux-mips@linux-mips.org
Subject: Re: [PATCH V2 05/15] genirq: Generic chip: Add big endian I/O accessors
Date: Thu, 30 Oct 2014 13:30:04 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.11.1410301233500.5308@nanos> (raw)
In-Reply-To: <14243833.KJsSScVrGS@wuerfel>
On Thu, 30 Oct 2014, Arnd Bergmann wrote:
> On Wednesday 29 October 2014 19:17:58 Kevin Cernekee wrote:
> > static LIST_HEAD(gc_list);
> > static DEFINE_RAW_SPINLOCK(gc_lock);
> >
> > +static int is_big_endian(struct irq_chip_generic *gc)
> > +{
> > + return !!(gc->domain->gc->gc_flags & IRQ_GC_BE_IO);
> > +}
> > +
> > static void irq_reg_writel(struct irq_chip_generic *gc,
> > u32 val, int reg_offset)
> > {
> > - writel(val, gc->reg_base + reg_offset);
> > + if (is_big_endian(gc))
> > + iowrite32be(val, gc->reg_base + reg_offset);
> > + else
> > + writel(val, gc->reg_base + reg_offset);
> > }
> >
>
> What I had in mind was to use indirect function calls instead, like
>
> #ifndef irq_reg_writel
> static inline void irq_reg_writel_le(u32 val, void __iomem *addr)
> {
> return writel(val, addr);
> }
> #endif
>
> #ifndef irq_reg_writel_be
> static inline void irq_reg_writel_be(u32 val, void __iomem *addr)
> {
> return iowrite32_be(val, addr);
> }
> #endif
>
>
> static inline void irq_reg_writel(struct irq_chip_generic *gc, u32 val, int reg_offset)
> {
> if (IS_ENABLED(CONFIG_GENERIC_IRQ_CHIP) &&
That's inside of the generic irq chip, so CONFIG_GENERIC_IRQ_CHIP is
always set when this is compiled.
> !IS_ENABLED(CONFIG_GENERIC_IRQ_CHIP_BE))
> return irq_reg_writel_le(val, gc->reg_base + reg_offset);
>
> if (IS_ENABLED(CONFIG_GENERIC_IRQ_CHIP) &&
> !IS_ENABLED(CONFIG_GENERIC_IRQ_CHIP_BE))
s/!// ?
> return irq_reg_writel_be(val, gc->reg_base + reg_offset);
I don't think the above will cover all combinations.
..._CHIP_BE ...CHIP_LE
N N ; Default behaviour: readl/writel
Y N ; ioread/write32be
N Y ; Default behaviour: readl/writel
Y Y ; Runtime selected
> return gc->writel(val, gc->reg_base + reg_offset);
> }
>
> This would take the condition out of the callers.
So you trade a conditional for an indirect call. Not sure what's more
expensive. The indirect call is definitely a smaller text footprint,
so we should opt for this.
Thanks,
tglx
next prev parent reply other threads:[~2014-10-30 12:30 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-30 2:17 [PATCH V2 00/15] genirq endian fixes; bcm7120/brcmstb IRQ updates Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 01/15] irqchip: Replace irq_reg_{readl,writel} with {readl,writel} Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 02/15] sh: Eliminate unused irq_reg_{readl,writel} accessors Kevin Cernekee
2014-10-30 9:00 ` Arnd Bergmann
2014-10-30 10:43 ` Thomas Gleixner
2014-10-30 10:48 ` Arnd Bergmann
2014-10-30 15:25 ` Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 03/15] genirq: Generic chip: Move irq_reg_{readl,writel} accessors into generic-chip.c Kevin Cernekee
2014-10-30 8:43 ` Thomas Gleixner
2014-10-30 9:06 ` Arnd Bergmann
2014-10-30 10:33 ` Thomas Gleixner
2014-10-30 11:50 ` Thomas Gleixner
2014-10-30 2:17 ` [PATCH V2 04/15] genirq: Generic chip: Change irq_reg_{readl,writel} arguments Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 05/15] genirq: Generic chip: Add big endian I/O accessors Kevin Cernekee
2014-10-30 9:21 ` Arnd Bergmann
2014-10-30 12:30 ` Thomas Gleixner [this message]
2014-10-30 12:40 ` Arnd Bergmann
2014-10-30 2:17 ` [PATCH V2 06/15] genirq: Generic chip: Optimize for fixed-endian systems Kevin Cernekee
2014-10-30 4:16 ` Brian Norris
2014-10-30 9:04 ` Arnd Bergmann
2014-10-30 2:18 ` [PATCH V2 07/15] irqchip: brcmstb-l2: Eliminate dependency on ARM code Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 08/15] irqchip: bcm7120-l2: Eliminate bad IRQ check Kevin Cernekee
2014-10-30 11:09 ` Sergei Shtylyov
[not found] ` <54521C65.8060603-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2014-10-30 19:24 ` Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 09/15] irqchip: Remove ARM dependency for bcm7120-l2 and brcmstb-l2 Kevin Cernekee
2014-10-30 11:10 ` Sergei Shtylyov
2014-10-30 11:24 ` Arnd Bergmann
2014-10-30 11:48 ` Sergei Shtylyov
2014-10-30 2:18 ` [PATCH V2 10/15] irqchip: bcm7120-l2: Make sure all register accesses use base+offset Kevin Cernekee
2014-10-30 9:12 ` Arnd Bergmann
2014-10-30 2:18 ` [PATCH V2 11/15] irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 12/15] irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 13/15] irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 14/15] irqchip: Decouple bcm7120-l2 from brcmstb-l2 Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 15/15] irqchip: bcm7120-l2: Enable big endian register accesses on BE kernels Kevin Cernekee
2014-10-30 9:03 ` Arnd Bergmann
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