From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Gleixner Subject: Re: [PATCH v3 1/6] irqchip: add support for Marvell Orion SoCs Date: Tue, 11 Jun 2013 15:45:25 +0200 (CEST) Message-ID: References: <1370536034-23956-1-git-send-email-sebastian.hesselbarth@gmail.com> <1370536034-23956-2-git-send-email-sebastian.hesselbarth@gmail.com> <51B7280B.7080604@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <51B7280B.7080604-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Sebastian Hesselbarth Cc: Andrew Lunn , Russell King , Jason Cooper , linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , John Stultz , Grant Likely , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Tue, 11 Jun 2013, Sebastian Hesselbarth wrote: > On 06/11/13 15:30, Thomas Gleixner wrote: > > On Tue, 11 Jun 2013, Thomas Gleixner wrote: > > > > > On Thu, 6 Jun 2013, Sebastian Hesselbarth wrote: > > > > > > > This patch adds an irqchip driver for the main interrupt controller > > > > found > > > > on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation). > > > > Corresponding device tree documentation is also added. > > > > > > > > Signed-off-by: Sebastian Hesselbarth > > > > > > Reviewed-by: Thomas Gleixner > > > > Second thoughts: > > > > > +static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc > > > *desc) > > > +{ > > > + struct irq_domain *d = irq_get_handler_data(irq); > > > + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq); > > > + u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & > > > + gc->mask_cache; > > > > In init you map the first irq of that chip and install the chain > > handler for it. Now if that first irq fires, isn't that set in the > > cause register as well? And what acks that first irq? > > It is "acked" by acking all unmasked bridge irqs. Ok. A comment would be nice. But what about the bit in of that first irq in the cause register? If it's set on entry you call generic_handle_irq() for that as well. So if it's set you need to mask it in stat. If not, then it wants a comment. Thanks, tglx