From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-178.mta0.migadu.com (out-178.mta0.migadu.com [91.218.175.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21B823B961B for ; Tue, 28 Jul 2026 07:13:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785222802; cv=none; b=SzOrbIpmwUS2F9uvFolYeD8HEvocT7AeX7XbGx2Zs7AU9tVVHJejAQuqbcWsjFaeCMO6d+LznTXIlCDAsAGEqFzlk7k4zv5AYOGPIq6+/J4iMmGfQkFCcr6Pj9vA0eWNRUTmUdgL55AFq3m3OMgD4yXHGj2NpM+GTlkXZfgWp/I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785222802; c=relaxed/simple; bh=mjKK88DT1Rk+iIX8hOsyWczc26G4O8r4eaKiEyE3SM8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ax+4X9tq8ukVs6qRX0czgwtswR2/HA7WMcDFWmx3RjcaTgKaxmbTdvLtPYKWYs2P9MCvc+f9ON+4ekdRzLkI8pr1PqWG+On3zv10des2yrMa+LHqesJc1+d/D8QFocBygWOOLXWy1/5utzU7om8tr/SUfd9eOiPEGqQsD8AdLd8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=mn9I/k6G; arc=none smtp.client-ip=91.218.175.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="mn9I/k6G" Date: Tue, 28 Jul 2026 09:13:09 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1785222795; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=WNJfnJCVGrisL2Q9GMR3UZa22fIREltooVK55uzyj4g=; b=mn9I/k6GlRH2HbTTrFSrjNw8RIgbs/VZ5oIbcBdsqrA1tPYm5Xmmzu35TT7Ap4TAkgSA7Y tLcBqyxcQ4v+eTXhmUCr7VssVj4xAPVOFuI9+cgaLmPYk0NmvSoJX/ZjkRUkKwHfVMnJ27 O1eQlRcCKvLpFij/c0SXv1+JUhOqFfw= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Richard Leitner To: Laurent Pinchart Cc: Conor Dooley , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Dave Stevenson , Alexander Stein , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, driver-core@lists.linux.dev Subject: Re: [PATCH RFC 1/2] dt-bindings: regmap: add common schema for no-sequential-read Message-ID: References: <20260722201622.GD648629@killaraus.ideasonboard.com> <525338f4-cad3-4acb-94c5-a4b71cde9c02@sirena.org.uk> <20260723154541.GA764516@killaraus.ideasonboard.com> <20260723-hamster-juniper-5697cacade96@spud> <20260723161048.GC767247@killaraus.ideasonboard.com> <20260724092812.GD712773@killaraus.ideasonboard.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260724092812.GD712773@killaraus.ideasonboard.com> X-Migadu-Flow: FLOW_OUT On Fri, Jul 24, 2026 at 12:28:12PM +0300, Laurent Pinchart wrote: > On Thu, Jul 23, 2026 at 08:55:18PM +0200, Richard Leitner wrote: > > On Thu, Jul 23, 2026 at 07:10:48PM +0300, Laurent Pinchart wrote: > > > On Thu, Jul 23, 2026 at 05:02:42PM +0100, Conor Dooley wrote: > > > > On Thu, Jul 23, 2026 at 06:45:41PM +0300, Laurent Pinchart wrote: > > > > > On Thu, Jul 23, 2026 at 01:01:11PM +0200, Richard Leitner wrote: > > > > > > On Wed, Jul 22, 2026 at 11:03:09PM +0100, Mark Brown wrote: > > > > > > > On Wed, Jul 22, 2026 at 11:58:46PM +0200, Richard Leitner wrote: > > > > > > > > > > > > > > > @Mark: I understood that if the fpga really intercepts the I2C bus, it > > > > > > > > should be modelled accordingly in device tree. But what would be the > > > > > > > > preferred implementation if both devices sit on the same I2C bus, but > > > > > > > > one is messing up some register reads on purpose? > > > > > > > > > > > > > > I think we would need to have a coherent understanding and description > > > > > > > of the actual issue to know how to describe it. > > > > > > > > > > > > Understood. I will try to figure out how the hardware is really wired > > > > > > and come back to you. > > > > > > > > > > Based on the information I have received so far, the FPGA is interposed > > > > > between the host and sensor. It could therefore be modelled in DT as > > > > > child of the I2C bus and a parent of the sensor. > > > > > > > > > > New version of some of the Vision Components modules have fixed the > > > > > multi-read bug, so we will still need a property in the FPGA DT node to > > > > > indicate if the quirk should be activated. > > > > > > > > Or come up with a compatible for the FPGA DT node that uniquely > > > > identifies the revision of the RTL in use. > > > > That's my preference for things that use some custom RTL that aren't > > > > configuration parameters. > > > > > > I'm afraid we won't be able to get that information. We have limited > > > visibility on the ecosystem of modules and what the FPGA does in each of > > > them. > > > > Thanks for the clarification. Should I continue working on this topic > > (i.e. modelling the FPGA as I2C controller with the sensor as a > > "subdevice")? Or do you want to take over Laurent? Do you have any other > > downstream work on the vc-mipi stuff, except the patches in your gitlab > > repo? > > I'm afraid I won't have time for the time being, as I will soon start my > summer holidays. The patches in the git tree you mentioned are all I > have. Ok. Thanks. Then I will give it a try. I did some more research on that module and it features a Lattice FPGA (LCMXO3LF-1300E) which to all of my measurement intercepts the I2C bus as expected. As it additionally manages the regulators my approach would be to implement a Multi-Function Devices (MFD) driver for it. The resulting DTS layout would then be something like: &i2c1 { fpga@10 { compatible = "visioncomponents,vc-mipi-controller"; reg = <0x10>; i2c-mux { compatible = "visioncomponents,vc-mipi-i2c-mux"; i2c@0 { reg = <0>; ov9282: camera-sensor@60 { compatible = "ovti,ov9282"; reg = <0x60>; ... }; }; }; vc_mipi_reg: regulator { compatible = "visioncomponents,vc-mipi-regulator"; }; }; }; Mark, Laurent, if that's incorrect or otherwise not acceptable, please reach out. Thanks a lot! regards;rl > > > I've additionally wrote "my Vision Components contact" an email asking > > for clarification of the I2C bus layout on the modules yesterday. If I > > get any new information from that path I will of course take it into account. > > > > Thanks a lot, Laurent! > > -- > Regards, > > Laurent Pinchart