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Tue, 28 Jul 2026 06:05:47 -0700 (PDT) Date: Tue, 28 Jul 2026 10:06:53 -0300 From: Marcelo Schmitt To: linux-iio@vger.kernel.org Cc: Marcelo Schmitt , conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org, marcelo.schmitt1@gmail.com Subject: Re: [PATCH v9 2/6] iio: adc: ltc2378: Add support for LTC2378-20 and similar ADCs Message-ID: References: <6cf0b5541cce4816877ebe754ef7fc2f0e30039c.1785186980.git.marcelo.schmitt@analog.com> <20260727214213.D377F1F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260727214213.D377F1F000E9@smtp.kernel.org> On 07/27, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [High] Holding CNV high during SPI transfer breaks 3-wire SPI wiring mode. > -- > > --- Patch [2]: [PATCH v9 2/6] iio: adc: ltc2378: Add support for LTC2378-20 and similar ADCs --- > commit 4d4231cee28f9742280dd61ed84f85cf3b4e0386 > Author: Marcelo Schmitt > > iio: adc: ltc2378: Add support for LTC2378-20 and similar ADCs > > This commit adds support for the Analog Devices LTC2378-20 and similar > analog-to-digital converters. > > > diff --git a/drivers/iio/adc/ltc2378.c b/drivers/iio/adc/ltc2378.c > > new file mode 100644 > > --- /dev/null > > +++ b/drivers/iio/adc/ltc2378.c > [ ... ] > > +static int ltc2378_convert_and_acquire(struct ltc2378_state *st) > > +{ > > + int ret; > > + > > + /* Cause a rising edge of CNV to initiate a new ADC conversion */ > > + gpiod_set_value_cansleep(st->cnv_gpio, 1); > > + fsleep(LTC2378_MAX_DATA_WAIT_US); > > + ret = spi_sync_transfer(st->spi, &st->xfer, 1); > > [Severity: High] > Does holding CNV high during the SPI transfer break 3-wire SPI wiring mode? > In 3-wire mode (where SDI is tied to GND), the SDO pin of the ADC remains in > a high-impedance state as long as the CNV pin is held high. No. > > Since the CNV pin remains high throughout the SPI transfer, could the SPI > controller clock in garbage data from a floating bus? No. That would only happen if the controller runs more SCLKs than the amount of precision/resolution bits (non-offload use case) but in those cases we right shift by _storage_bits - _real_bits, discarding any potential unwanted noise. > > Would lowering CNV after the fsleep() wait and before calling > spi_sync_transfer() correctly enable SDO for 3-wire mode while remaining > compatible with 4-wire (CS) mode? These devices don't have a CS pin. SDI is tied to GND in the currently supported wiring configuration (single device normal mode). There is no SPI 4-wire mode. > > > + gpiod_set_value_cansleep(st->cnv_gpio, 0); > > + > > + return ret; > > +} > [ ... ] > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/cover.1785186980.git.marcelo.schmitt@analog.com?part=2