From: Inochi Amaoto <inochiama@gmail.com>
To: Junhui Liu <junhui.liu@pigmoral.tech>,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Yixun Lan <dlan@kernel.org>,
Inochi Amaoto <inochiama@outlook.com>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Guodong Xu <guodong@riscstar.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
Conor Dooley <conor.dooley@microchip.com>,
Inochi Amaoto <inochiama@gmail.com>
Subject: Re: [PATCH RFC 5/7] irqchip/aclint-sswi: Add generic riscv,aclint-sswi match
Date: Wed, 29 Jul 2026 06:14:59 +0800 [thread overview]
Message-ID: <amkprTVtjkRVEo7G@inochi.infowork> (raw)
In-Reply-To: <20260729-k3-aclint-v1-5-aef88614d3a5@pigmoral.tech>
On Wed, Jul 29, 2026 at 12:36:31AM +0800, Junhui Liu wrote:
> Add match entry for the generic "riscv,aclint-sswi" compatible string.
> This allows future SoCs with standard ACLINT SSWI implementations to
> directly reuse the driver via the generic fallback compatible (at least
> until hardware-specific quirks are identified).
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> drivers/irqchip/irq-aclint-sswi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint-sswi.c
> index ca06efd86fa1..2bd40c3ea288 100644
> --- a/drivers/irqchip/irq-aclint-sswi.c
> +++ b/drivers/irqchip/irq-aclint-sswi.c
> @@ -179,6 +179,7 @@ static int __init generic_aclint_sswi_early_probe(struct device_node *node,
> }
> IRQCHIP_DECLARE(mips_p8700_sswi, "mips,p8700-aclint-sswi", generic_aclint_sswi_early_probe);
> IRQCHIP_DECLARE(nuclei_ux900_sswi, "nuclei,ux900-aclint-sswi", generic_aclint_sswi_early_probe);
> +IRQCHIP_DECLARE(riscv_sswi, "riscv,aclint-sswi", generic_aclint_sswi_early_probe);
>
Again, use vendor specific name for irqchip declaration.
> /* THEAD variant */
> #define THEAD_C9XX_CSR_SXSTATUS 0x5c0
>
> --
> 2.55.0
>
Reagrds,
Inochi
next prev parent reply other threads:[~2026-07-28 22:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 16:36 [PATCH RFC 0/7] spacemit: k3: Replace bad CLINT node with ACLINT nodes Junhui Liu
2026-07-28 16:36 ` [PATCH RFC 1/7] dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3 Junhui Liu
2026-07-28 22:13 ` Inochi Amaoto
2026-07-28 16:36 ` [PATCH RFC 2/7] dt-bindings: interrupt-controller: thead,c900-aclint-mswi: " Junhui Liu
2026-07-28 16:36 ` [PATCH RFC 3/7] dt-bindings: interrupt-controller: thead,c900-aclint-sswi: " Junhui Liu
2026-07-28 16:36 ` [PATCH RFC 4/7] dt-bindings: timer: sifive,clint: Mark spacemit,k3-clint as deprecated Junhui Liu
2026-07-28 16:36 ` [PATCH RFC 5/7] irqchip/aclint-sswi: Add generic riscv,aclint-sswi match Junhui Liu
2026-07-28 22:14 ` Inochi Amaoto [this message]
2026-07-28 16:36 ` [PATCH RFC 6/7] riscv: dts: spacemit: k3: Fix SSWI node misidentified as CLINT Junhui Liu
2026-07-28 16:36 ` [PATCH RFC 7/7] riscv: dts: spacemit: k3: Add ACLINT MSWI and MTIMER nodes Junhui Liu
2026-07-28 22:15 ` Inochi Amaoto
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