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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 00721157ae682-81fcd0d70besm54676927b3.31.2026.08.03.07.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:37:02 -0700 (PDT) Date: Mon, 3 Aug 2026 10:37:00 -0400 From: Brian Masney To: Louis-Alexis Eyraud Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran , Chen-Yu Tsai , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org Subject: Re: [PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets Message-ID: References: <20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com> <20260801-mt8189-clocks-system-base-v5-10-ac4410697cc2@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260801-mt8189-clocks-system-base-v5-10-ac4410697cc2@collabora.com> User-Agent: Mutt/2.4.0 (2026-06-19) On Sat, Aug 01, 2026 at 01:20:56PM +0200, Louis-Alexis Eyraud wrote: > Currently, the register offset to handle BAR reset, for PLLs that > support it, is hardcoded to CON0. > On MT8189 SoC, there are separate status, set and clr registers to > handle this, so differents offsets are needed. > > Add the new fields for offsets and addresses to the MTK PLL data > structure and modify mtk_clk_register_pll_ops function to compute the > new register addresses so they are available for clock operation usage. > > Also, replace reset BAR address computing by its computed address > from MTK PLL data structure in prepare/unprepare callbacks. > > Signed-off-by: Louis-Alexis Eyraud Reviewed-by: Brian Masney