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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-66948fcb3acsm5643561d50.10.2026.08.03.07.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:44:17 -0700 (PDT) Date: Mon, 3 Aug 2026 10:44:15 -0400 From: Brian Masney To: Louis-Alexis Eyraud Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran , Chen-Yu Tsai , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org Subject: Re: [PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs Message-ID: References: <20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com> <20260801-mt8189-clocks-system-base-v5-13-ac4410697cc2@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260801-mt8189-clocks-system-base-v5-13-ac4410697cc2@collabora.com> User-Agent: Mutt/2.4.0 (2026-06-19) Hi Louis-Alexis, On Sat, Aug 01, 2026 at 01:20:59PM +0200, Louis-Alexis Eyraud wrote: > MT8189 SoC uses a new combination of status and set/clr registers to > control its PLL enable state and perform BAR reset, that are different > than the current default clock prepare/unprepare operations are using. > > Add new set of PLL clock operations to support this logic that relies > on the following registers for prepare/unprepare operations: > - en/en_set/en_clr, rather than en register, for PLL enable > control > - rst_bar/rst_bar_set/rst_bar_clr, rather than default rst_bar > register for BAR reset control > > Also, handle rst_bar register setting/clearing with a timeout, to > verify the operation was correctly performed. > > Signed-off-by: Louis-Alexis Eyraud > --- > drivers/clk/mediatek/clk-pll.c | 66 ++++++++++++++++++++++++++++++++++++++++++ > drivers/clk/mediatek/clk-pll.h | 5 ++++ > 2 files changed, 71 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index 9a197a657dce..3118f68aa9ac 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -32,6 +33,7 @@ > #define INTEGER_BITS 7 > > #define PLL_STABILIZATION_DELAY 20 /* in us */ > +#define RST_BAR_TIMEOUT 20 /* in us */ > > int mtk_pll_is_prepared(struct clk_hw *hw) > { > @@ -301,6 +303,60 @@ void mtk_pll_unprepare(struct clk_hw *hw) > mtk_pll_power_off(pll); > } > > +int mtk_pll_prepare_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); > + u32 val = 0; > + int ret; > + > + mtk_pll_power_on(pll); > + > + writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); > + > + __mtk_pll_tuner_enable(pll); > + > + udelay(PLL_STABILIZATION_DELAY); > + > + if (pll->data->flags & HAVE_RST_BAR) { > + writel(pll->data->rst_bar_mask, pll->rst_bar_set_addr); > + > + ret = readl_poll_timeout(pll->rst_bar_addr, val, > + (val & pll->data->rst_bar_mask), 1, > + RST_BAR_TIMEOUT); > + if (ret) { > + mtk_pll_unprepare_setclr(hw); > + return ret; > + } > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(mtk_pll_prepare_setclr); > + > +void mtk_pll_unprepare_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); > + u32 val = 0; > + > + if (pll->data->flags & HAVE_RST_BAR) { > + writel(pll->data->rst_bar_mask, pll->rst_bar_clr_addr); > + > + /* ignore return code to continue unpreparing the PLL if > + * a error occurs on register read poll. Use proper kernel comment: /* * Ignore return code... */ Also s/a error/an error/ With that fixed: Reviewed-by: Brian Masney