On Tue, Jul 21, 2026 at 10:29:49AM +0200, Herve Codina (Schneider Electric) wrote:
> In the Renesas RZ/N1 SoCs family, two timers block are available.
> 
> Each block contains 8 timers composed of 6 16-bits timers and 2 32-bits
> timers.
> 
> Each timer has its own interrupt line.
> 
> Describe those timers blocks.
> 

Nits: Maybe delete the empty lines and write all this in one paragraph?

> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Same testing as in patch 2, same comment about 0x400 reg-size as in
patch 1.