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Tue, 11 Aug 2026 02:36:23 -0700 (PDT) Date: Tue, 11 Aug 2026 17:36:13 +0800 From: Yu-Chien Peter Lin To: "Rob Herring (Arm)" Cc: pjw@kernel.org, zhangchunyan@iscas.ac.cn, conor+dt@kernel.org, greentime.hu@sifive.com, robin.randhawa@sifive.com, dfustini@oss.tenstorrent.com, raymond.mao@riscstar.com, dave.patel@riscstar.com, pincheng.plct@isrc.iscas.ac.cn, linux-kernel@vger.kernel.org, darshan.prajapati@einfochips.com, linux-riscv@lists.infradead.org, junhui.liu@pigmoral.tech, akpm@linux-foundation.org, dlan@kernel.org, jim.shu@sifive.com, devicetree@vger.kernel.org, luxu.kernel@bytedance.com, krzk+dt@kernel.org, zong.li@sifive.com, anup@brainfault.org, michal.simek@amd.com, scott@riscstar.com, alex@ghiti.fr, samuel.holland@sifive.com, aou@eecs.berkeley.edu, pawandeep.oza@oss.qualcomm.com, palmer@dabbelt.com, nick.hu@sifive.com Subject: Re: [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Message-ID: References: <20260729163908.249838-1-peter.lin@sifive.com> <20260729163908.249838-4-peter.lin@sifive.com> <178534841831.3259884.2854898669055783798.robh@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <178534841831.3259884.2854898669055783798.robh@kernel.org> Hi Rob, On Wed, Jul 29, 2026 at 01:07:00PM -0500, Rob Herring (Arm) wrote: > > On Thu, 30 Jul 2026 00:39:08 +0800, Yu-Chien Peter Lin wrote: > > Add YAML binding schema for the SiFive wgChecker, a programmable > > access controller integrated in the interconnect fabric of RISC-V > > Worlds-capable SoCs. > > > > wgChecker enforces World ID (WID) based access control on downstream > > bus transactions. Each checker slot encodes a 2-bit permission field > > per WID (read/write), enabling fine-grained memory partitioning and > > device isolation between execution contexts. Violations are reported > > via bus errors, interrupts, or both, selectable and lockable per slot. > > > > The binding registers wgChecker as an access-controllers provider. > > Consumers (i.e. its protected device) reference it via the standard > > access-controllers phandle to declare their access requirements. > > > > Also document the sifive,trustedwid property for the /cpus node, > > identifying the privileged WID authorized to configure all checkers > > on the platform. > > > > Link: https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf > > Signed-off-by: Yu-Chien Peter Lin > > Reviewed-by: Zong Li > > Reviewed-by: Jim Shu > > --- > > .../devicetree/bindings/riscv/worlds.yaml | 9 + > > .../bindings/sifive/sifive,wgchecker2.yaml | 356 ++++++++++++++++++ > > 2 files changed, 365 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/sifive/sifive,wgchecker2.example.dtb: uart@1c1000 (ns16550a): $nodename:0: 'uart@1c1000' does not match '^serial(@.*)?$' > from schema $id: http://devicetree.org/schemas/serial/8250.yaml > Documentation/devicetree/bindings/sifive/sifive,wgchecker2.example.dtb: uart@1c1000 (ns16550a): Unevaluated properties are not allowed ('access-controllers', 'reg-names' were unexpected) > from schema $id: http://devicetree.org/schemas/serial/8250.yaml Will fix. Thanks, Peter Lin