From: Frank Li <Frank.li@oss.nxp.com>
To: Laurentiu Mihalcea <laurentiumihalcea111@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
elena.popa@nxp.com, cosmin.stoica@nxp.com,
Pengutronix Kernel Team <kernel@pengutronix.de>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] arm64: dts: freescale: add MR-NAVQ95 basic board support
Date: Tue, 25 Aug 2026 09:25:00 -0500 [thread overview]
Message-ID: <ao2lvM8NCV3XmArL@SMW015318> (raw)
In-Reply-To: <20260825120812.2152-3-laurentiumihalcea111@gmail.com>
On Tue, Aug 25, 2026 at 05:08:12AM -0700, Laurentiu Mihalcea wrote:
> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>
> Add basic support for NXP's MR-NAVQ95 board. This board is designed for
> robotics applications (e.g. drones, rovers, humanoids, etc..) and has the
> following hardware feats (list is not exhaustive):
>
> * based on i.MX95 19x19 SoC
> * 64GB eMMC
> * up to 16GB of LPDDR5 memory
> * 1 x USB 2.0 TypeC
> * 1 x USB 3.0 TypeC
> * 1 x RJ45 port with RTL8211 PHY
>
> The support targets revision B of the board.
>
> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/imx95-navq.dts | 267 +++++++++++++++++++
> 2 files changed, 268 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx95-navq.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 95ae85ab4adf..4c5ef83cd857 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -712,6 +712,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx95-navq.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596la-mba95xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx95-navq.dts b/arch/arm64/boot/dts/freescale/imx95-navq.dts
> new file mode 100644
> index 000000000000..f7ddc39f9b21
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-navq.dts
> @@ -0,0 +1,267 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2026 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx95.dtsi"
> +
> +/ {
> + model = "NXP MR-NAVQ95";
> + compatible = "fsl,imx95-navq", "fsl,imx95";
> +
> + aliases {
> + ethernet0 = &enetc_port0;
> + mmc0 = &usdhc1;
> + mmc1 = &usdhc2;
> + serial0 = &lpuart1;
> + };
> +
> + chosen {
> + stdout-path = &lpuart1;
> + };
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> + regulator-name = "VDD_SD2_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + off-on-delay-us = <12000>;
> + };
> +};
> +
> +&edma1 {
> + /* owned by M7 */
> + status = "reserved";
> +};
> +
> +&edma2 {
> + /* channels 30-63 owned by M7 */
> + dma-channels = <30>;
> +};
> +
> +&enetc_port0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enetc0>;
> + phy-handle = <ðphy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +};
> +
> +&lpi2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpi2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + i2c3_gpio_expander_21: gpio-expander@21 {
> + compatible = "nxp,pcal6408";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3_gpio_expander_21>;
> + };
> +};
> +
> +&lpuart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&netc_blk_ctrl {
> + status = "okay";
> +};
> +
> +&netc_emdio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_emdio>;
> + status = "okay";
> +
> + ethphy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-id001c.c916";
> + reg = <1>;
> + reset-gpios = <&i2c3_gpio_expander_21 1 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + reset-deassert-us = <80000>;
> + realtek,clkout-disable;
> + };
> +};
> +
> +&scmi_iomuxc {
> + pinctrl_emdio: emdiogrp {
> + fsl,pins = <
> + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e
> + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
> + >;
> + };
> +
> + pinctrl_enetc0: enetc0grp {
> + fsl,pins = <
> + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
> + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
> + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
> + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
> + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
> + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
> + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
> + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
> + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
> + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
> + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
> + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
> + >;
> + };
> +
> + pinctrl_i2c3_gpio_expander_21: i2c3gpioexpander21grp {
> + fsl,pins = <
> + IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e
> + >;
> + };
> +
> + pinctrl_lpi2c3: lpi2c3grp {
> + fsl,pins = <
> + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
> + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
> + >;
> + };
> +
> + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
> + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
if the value is the same 100mzh, 200mzh and default
Needn't duplicate it.
Just
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
Frank
> +
> + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + pinctrl-3 = <&pinctrl_usdhc1>;
> + bus-width = <8>;
> + non-removable;
> + no-sdio;
> + no-sd;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + bus-width = <4>;
> + status = "okay";
> +};
> --
> 2.53.0
>
>
next prev parent reply other threads:[~2026-08-25 14:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 12:08 [PATCH 0/2] Introduce basic support for MR-NAVQ95 Laurentiu Mihalcea
2026-08-25 12:08 ` [PATCH 1/2] dt-bindings: arm: fsl: add MR-NAVQ95 board Laurentiu Mihalcea
2026-08-25 16:51 ` Conor Dooley
2026-08-25 12:08 ` [PATCH 2/2] arm64: dts: freescale: add MR-NAVQ95 basic board support Laurentiu Mihalcea
2026-08-25 14:25 ` Frank Li [this message]
2026-08-25 21:52 ` Fabio Estevam
2026-08-26 8:24 ` Laurentiu Mihalcea
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ao2lvM8NCV3XmArL@SMW015318 \
--to=frank.li@oss.nxp.com \
--cc=Frank.Li@nxp.com \
--cc=conor+dt@kernel.org \
--cc=cosmin.stoica@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=elena.popa@nxp.com \
--cc=festevam@gmail.com \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=krzk+dt@kernel.org \
--cc=laurentiumihalcea111@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox