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Fri, 21 Aug 2026 03:46:17 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395c4c37996sm2558815a91.16.2026.08.21.03.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 03:46:16 -0700 (PDT) Date: Fri, 21 Aug 2026 16:16:08 +0530 From: Abhinaba Rakshit To: Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 6/6] arm64: dts: qcom: lemans: Add OPP-table for ICE UFS device node Message-ID: References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-6-1cebc8b3275b@oss.qualcomm.com> <71f41225-226e-42b2-87e4-2c8b082aeae7@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <71f41225-226e-42b2-87e4-2c8b082aeae7@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX9wt9bOAo+cEO ZmhiVgpKSQMVssimFhrO+u41P4KHKcvGXE1ddSD07cXkyviTr+6BvuSN6hwx656vIVYP/+PYVoW ieaaPMkejD4NqU0orKiI4FUC1yOCReu8cevbmHb2ICR7oKtgNbIRlDlC7hearchnTRYBypMgfnY 6PARaOhjXCnGiLIm/OSt6M30kaDhjPUof2MCKuYKo+mJCMuCf/dTvOl/GnwbT548Glbmr+UCSiB McYqW80TLmRRLV9G6N603GbocIJ1AYrioPhzFZp4hX08Fr39xx6cBp6+cik06cm1vlO4XtvbbR2 UusSUo/6O1zB/wuodhi7TIrN4P/hP4hA2TuOaRRq6lvizz4UFdhnNZaUP4qTibIpFc+AF6mQeEu bHtc3cPZr4gkxsmCNmV8XX54dmC/VFjW6HeHy9O0oIibw2+BdRK2D26G+DQUBZMSA6BHzj2dkXp 84WsKuBnZfbAkYSX0Ag== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfXzzz8I8X9n8zX dC92Pxmy+eJGxFecV/dLM/ZSXvR95JBYj+PP//3t2Xq8YzzhKCKlyxSn9LKoRLoisEKxFMK9uml unBttQvtu2lE6PnIdFSCACL2VRzwfxI= X-Proofpoint-ORIG-GUID: WBiIXCWNyErofYmFh-kKHl6HLGMzrNMu X-Authority-Analysis: v=2.4 cv=BJyDalQG c=1 sm=1 tr=0 ts=6a882c7c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=oKECPZB_XDwA82e_iN8A:9 a=CjuIK1q_8ugA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: WBiIXCWNyErofYmFh-kKHl6HLGMzrNMu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210081 On Thu, Jun 18, 2026 at 03:05:27PM +0200, Konrad Dybcio wrote: > On 6/8/26 11:47 PM, Abhinaba Rakshit wrote: > > Qualcomm Inline Crypto Engine (ICE) platform driver now supports > > an optional OPP-table. > > > > Add OPP-table for ICE UFS device nodes for LeMans platform. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > arch/arm64/boot/dts/qcom/lemans.dtsi | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > > index 353a6e6fd3acb22ef228bee340212b8b2c300957..f100d706edde465730873702f0b0a00b44050c23 100644 > > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > > @@ -3109,6 +3109,32 @@ ice: crypto@1d88000 { > > clock-names = "core", > > "iface"; > > power-domains = <&gcc UFS_PHY_GDSC>; > > + > > + operating-points-v2 = <&ice_opp_table>; > > + > > + ice_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-75000000 { > > + opp-hz = /bits/ 64 <75000000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > + > > + opp-150000000 { > > + opp-hz = /bits/ 64 <150000000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > + > > + opp-300000000 { > > + opp-hz = /bits/ 64 <300000000>; > > + required-opps = <&rpmhpd_opp_nom>; > > + }; > > + > > + opp-600000000 { > > + opp-hz = /bits/ 64 <600000000>; > > + required-opps = <&rpmhpd_opp_nom>; > > + }; > > Analogous question for both pairs of frequencies > The same rationale applies to LeMans: its UFS controller supports 75 MHz and 600 MHz. These ICE OPPs are retained to better synchronize the ICE and UFS clock frequencies, even though both operate at the same power level. Abhinaba Rakshit