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> if (!hci->quirks && platform_get_device_id(pdev)) > hci->quirks = platform_get_device_id(pdev)->driver_data; > + if (hci->quirks & HCI_QUIRK_DMA_64BIT) { > + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); dma_set_mask_and_coherent() never return fail when bit mask >= 32 if (hci->quirks & HCI_QUIRK_DMA_64BIT) dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); Frank > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "cannot set DMA mask\n"); > + } > > ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); > if (ret < 0) > diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h > index f50fc1e22a85..2110f806a53c 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/hci.h > +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h > @@ -178,6 +178,7 @@ struct i3c_hci_dev_data { > #define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW resets after DMA abort */ > #define HCI_QUIRK_DMA_REQUIRES_HC_ABORT BIT(9) /* Use HC_CONTROL ABORT to abort DMA */ > #define HCI_QUIRK_DAT_INDEX_IS_ADDR BIT(10) /* DAT entries are indexed by device address */ > +#define HCI_QUIRK_DMA_64BIT BIT(11) /* Controller DMA supports 64-bit addressing */ > > /* global functions */ > void mipi_i3c_hci_resume(struct i3c_hci *hci); > > -- > 2.34.1 >