On Thu, Aug 20, 2026 at 06:16:31PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
> controller is similar to RZ/G2L but has five clocks (core, clkh,
> cd, aclkm, aclks) and three resets (rst, axim, axis), so update the
> clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
> It has an internal divider for all modes except HS400, and a 2048-bit
> divider compared to 512 on others.
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Looks good to me. Adding new SoCs might turn into an adventure game with
serious logic puzzles, though. Not your fault, of course.

DT checks pass here as well.

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>