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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33450e140d3sm36413401eec.4.2026.09.09.01.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 01:41:41 -0700 (PDT) Date: Wed, 9 Sep 2026 16:41:35 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Message-ID: References: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> <20260907-nords_dprx-v1-1-d472af3f01b1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260907-nords_dprx-v1-1-d472af3f01b1@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=ItAutr/g c=1 sm=1 tr=0 ts=6aa11bc7 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=YV3RISIrYtFRF6gnviEA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 a=CjuIK1q_8ugA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDA5NSBTYWx0ZWRfX7c/LHVaeTc5V CsyQI1rXulz0YccIfauX2pOIHVKDO8Hc6z0ajOJCUL+pKxRf4EhlXvebkEvucP1jlYdSe6KUiyO 8o9s/DCCPlwJB1c/PQLXqVDuOFNggJ4= X-Proofpoint-ORIG-GUID: budH1DJnIfHUeh5MNL2PYJJaDdEpOvtR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDA5NSBTYWx0ZWRfX/iu1/ljlSYoh qYROSjNhzl4+uW7tVCw3NR5vX0ikfihtn2nTGgAM//O1yjbE7eEhbF0bVTevTvjCU0/3ZoL1flA YgRrOJ6FoSnCBCPCP6rSU37KyEpxCjYu1dATvoZ6PYL2mqo/nONfjAX0jVWTXdzHZMFh7EvsFFM lNhdY7y0Plp0AVs2ZPxDexNyPR7nfm4nobP1wC/MdHrEIjeFzgYSeGyo2AzWKcXsM279jVJi6L2 y/N4vEuWp8T5K+p4eQ9IFzzyBKGF4z+2qKfL+gZnW9YBiCOm5X7/YCYkabOMF1dkiaXaSEU1MWY OxK6LNR/irr6r9sVqXqElb3z0MDQGjtwl3AkCiQIjsSPp0Cw9HnrOwEPpVYOMnZ+7JnBorBulHQ fGIZxbnuIi7jn478CwyYJ6QRWDWJK+6VofJK02HTtcYQAFqpTMyuZ/709f/wjiKCVI/HVQ7l2o2 grLXHcdl1CxnX1XMQBg== X-Proofpoint-GUID: budH1DJnIfHUeh5MNL2PYJJaDdEpOvtR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-08_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090095 On Mon, Sep 07, 2026 at 01:56:13PM +0530, Taniya Das wrote: > On some PLLs the PLL_ALPHA_VAL register has been increased to 28 bits to > carry the fractional word at a finer resolution, for example the > ZONDA_OLE instances on the Qualcomm Nord DPRX. The alpha-PLL core, > however, derives the ALPHA_VAL width solely from the register-map layout > and can only express 16 or 40 bits, so it programs and reads back the > 28-bit configuration at the wrong scale on both the set_rate/slew and > recalc_rate paths, making the PLL lock to and report the wrong rate. > > Add a way to identify the wider register: an optional alpha_width field > in struct clk_alpha_pll that, when non-zero, supersedes the > register-derived width. This feeds pll_alpha_width(), so the recalc_rate > and round_rate math scale the fractional word correctly, and the Zonda > set_rate L-adjust MSB check is derived from the active width instead of > a hardcoded BIT(15). PLLs that leave the field zero retain the previous > behaviour. > > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/clk-alpha-pll.c | 7 ++++--- > drivers/clk/qcom/clk-alpha-pll.h | 3 +++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 60173b076cc5f16bb55343a1d1136eb07f3c050f..981f973da02f379832fdc0cded3f2b4cae5879e4 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -382,8 +382,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) > > #define pll_alpha_width(p) \ > - ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ > - ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) > + ((p)->alpha_width ? (p)->alpha_width : \ > + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ > + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)) The inner ternary kept its original indentation, so the two continuation lines are now misaligned relative to the new outer ternary. Worth re-wrapping. > > #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) > > @@ -2290,7 +2291,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, > if (ret < 0) > return ret; > > - if (a & PLL_ALPHA_MSB) PLL_ALPHA_MSB becomes dead code then. Shawn > + if (a & BIT(alpha_width - 1)) > zonda_pll_adjust_l_val(rate, prate, &l); > > regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h > index 3a2157bebc52cd15f55381a068953f21be18f6bb..ab3b4f4fc7501df0fa3f59d741d64646383e4cfd 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.h > +++ b/drivers/clk/qcom/clk-alpha-pll.h > @@ -86,6 +86,8 @@ struct pll_vco { > * struct clk_alpha_pll - phase locked loop (PLL) > * @offset: base address of registers > * @regs: alpha pll register map (see @clk_alpha_pll_regs) > + * @alpha_width: optional override of the ALPHA_VAL width in bits; > + * 0 means derive the width from @regs > * @config: array of pll settings > * @vco_table: array of VCO settings > * @num_vco: number of VCO settings in @vco_table > @@ -95,6 +97,7 @@ struct pll_vco { > struct clk_alpha_pll { > u32 offset; > const u8 *regs; > + u32 alpha_width; > > const struct alpha_pll_config *config; > const struct pll_vco *vco_table; > > -- > 2.34.1 > >