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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c331aef9bsm12287653eec.25.2026.09.20.06.16.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 06:16:15 -0700 (PDT) Date: Sun, 20 Sep 2026 21:16:09 +0800 From: Shawn Guo To: Vishnu Reddy Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] arm64: dts: qcom: nord: Add iris video node Message-ID: References: <20260919-nord-iris-v1-0-94428761ec06@oss.qualcomm.com> <20260919-nord-iris-v1-2-94428761ec06@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260919-nord-iris-v1-2-94428761ec06@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDE5MyBTYWx0ZWRfX68OeM1iKBItP x+6yoRELczK/SD+BrJyBzCJiiy3GhbBaCbQdOyoMI091t1U2SX+b5dIeqCxQ+I20VYjVInhQ1pf iIPNSJ9PKy3Mkt0kfu4LJjzJyD4v90LgjpZABBOOUMqVZti4hWuFwWMpN41IgAM8tpkqF3umNyf xQFW8zoFuMZIU4npXiVpwQbJ8mpS07iUS9oiPc0d61toH4E4+ZrCp17BMOPjijtDQOgRNVgPx4+ ATdWALbej1XucsFExYYmt/GkaYEUscpZ8BcIQYJvaPpF7ounrthl7x5JsyMapgS22+ExDuNUJar MT+AjnWkKdUbW+opK0AON1PHOCMNBMsFPR265xYxnnao8nFPhTcZgoGTH9T9dyR/oiIwYoyRuW4 O3hEUNe4TqxxxLkJIJedptc841TOXOPxK4Oe0d/Zn0M79MPL5etAkVnG7b4noGhIQ6bGlqbrF/W dmb4mTXLH1PJTbPPBSA== X-Authority-Analysis: v=2.4 cv=RMQmjIi+ c=1 sm=1 tr=0 ts=6aafdca1 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=cpf97Ptf5-OE3Sj05EoA:9 a=CjuIK1q_8ugA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: b1WPCApRpbWO7AzePzJ6llNEHIGVKBtU X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDE5MyBTYWx0ZWRfXzf9ZE00qISgv eHp0nzSW8gF571k5YCbkZlSNAY8Vxkt2lZHn5tTd/bSOxc8N8l+oOxplfx7DC/DoXcIJJ93DPl3 KLS6qll0SnxkHsu3U1yRinTsa03Uk7c= X-Proofpoint-GUID: b1WPCApRpbWO7AzePzJ6llNEHIGVKBtU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_04,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 adultscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200193 On Sat, Sep 19, 2026 at 10:14:56AM +0530, Vishnu Reddy wrote: > Add iris video codec to nord SoC, which comes with significantly different > powering up sequence than previous platforms, thus different clocks and > resets. > > Signed-off-by: Vishnu Reddy > --- > arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 114 ++++++++++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi > index 74f4e6be8652..03f827f3e5fc 100644 > --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi > +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi > @@ -1428,6 +1428,120 @@ camcc: clock-controller@9ce0000 { > #power-domain-cells = <1>; > }; > > + iris: video-codec@aa00000 { > + compatible = "qcom,nord-iris", "qcom,glymur-iris"; > + reg = <0x0 0x0aa00000 0x0 0xf0000>; nord-embedded.dtsi is a place to accommodate Nord Embedded variant specific resource descriptions, like clock, regulator, pinctrl, interconnect, power domain, PHY, etc. The rest of descriptions should go to nord.dtsi, like reg, interrupts, iommu, dma, etc. Shawn > + > + clocks = <&nwgcc NW_GCC_VIDEO_AXI0_CLK>, > + <&videocc VIDEO_CC_MVS0C_CLK>, > + <&videocc VIDEO_CC_MVS0_CLK>, > + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK>, > + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, > + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, > + <&nwgcc NW_GCC_VIDEO_AXI1_CLK>, > + <&videocc VIDEO_CC_MVS1_CLK>, > + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; > + clock-names = "core_iface", > + "core", > + "vcodec0_core", > + "vcodec0_iface", > + "core_freerun", > + "vcodec0_core_freerun", > + "vcodec1_iface", > + "vcodec1_core", > + "vcodec1_core_freerun"; > + > + dma-coherent; > + > + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_VIDEO_MVP0 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "cpu-cfg", > + "video-mem"; > + > + interrupts = ; > + > + memory-region = <&video_mem>; > + > + operating-points-v2 = <&iris_opp_table>; > + > + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, > + <&videocc VIDEO_CC_MVS0_GDSC>, > + <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&videocc VIDEO_CC_MVS1_GDSC>; > + power-domain-names = "venus", > + "vcodec0", > + "mxc", > + "mmcx", > + "vcodec1"; > + > + resets = <&nwgcc NW_GCC_VIDEO_AXI0_CLK_ARES>, > + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK_ARES>, > + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, > + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, > + <&nwgcc NW_GCC_VIDEO_AXI1_CLK_ARES>, > + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; > + reset-names = "core_bus", > + "vcodec0_bus", > + "core", > + "vcodec0_core", > + "vcodec1_bus", > + "vcodec1_core"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + dma-ranges = <0x0 0x0 0x0 0xffe00000>; > + > + status = "disabled"; > + > + non-pixel { > + iommus = <&apps_smmu_1 0x0940 0x20>, > + <&apps_smmu_1 0x0944 0x0>, > + <&apps_smmu_1 0x0960 0x20>; > + iommu-ranges = <0x25800000 0xda600000>; > + }; > + > + pixel { > + iommus = <&apps_smmu_1 0x0943 0x0>; > + }; > + > + iris_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-240000000 { > + opp-hz = /bits/ 64 <240000000 240000000 360000000>; > + required-opps = <&rpmhpd_opp_svs>, > + <&rpmhpd_opp_svs>; > + }; > + > + opp-435000000 { > + opp-hz = /bits/ 64 <435000000 435000000 652500000>; > + required-opps = <&rpmhpd_opp_svs_l1>, > + <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000 480000000 720000000>; > + required-opps = <&rpmhpd_opp_svs_l1>, > + <&rpmhpd_opp_nom>; > + }; > + > + opp-533333333 { > + opp-hz = /bits/ 64 <533333333 533333333 800000000>; > + required-opps = <&rpmhpd_opp_svs_l1>, > + <&rpmhpd_opp_turbo>; > + }; > + > + opp-560000000 { > + opp-hz = /bits/ 64 <560000000 560000000 840000000>; > + required-opps = <&rpmhpd_opp_nom>, > + <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + > videocc: clock-controller@aaf0000 { > compatible = "qcom,nord-videocc"; > reg = <0x0 0x0aaf0000 0x0 0x10000>; > > -- > 2.34.1 > >