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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f2a3e24asm3822296c88.11.2026.09.22.03.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 03:26:53 -0700 (PDT) Date: Tue, 22 Sep 2026 18:26:47 +0800 From: Shawn Guo To: Jie Gan Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: dts: qcom: nord: add CoreSight debug nodes Message-ID: References: <20260922100850.527109-1-shengchao.guo@oss.qualcomm.com> <20260922100850.527109-3-shengchao.guo@oss.qualcomm.com> <63c1fa59-1a2d-4c39-b0df-ca7c00d2e535@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <63c1fa59-1a2d-4c39-b0df-ca7c00d2e535@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDE1MCBTYWx0ZWRfX0mzfFr7E889N RNtH14GMwFyEPYp3gEP4S1V/xtxz0m/mhL30yCyX3kQ0yAjOjXMXJie0oNZ2BhoZ/Nb24W0ReV2 R+N6vGMJZaaQpgiE7P6n/B7BxEk+tC9UxWqVnX9UIzmaXDXrr8jS01VPWDobjNHVOylU+JRjxSO IZCGg2XhNehkdZTOhRDtj6pXJX04qicxf9r4AKGbZcwhc58x7ZnGuLiNKtWtuvbl5GCZzb4bT5G 3hb1u54gXBxYPVMgvMPGs228PrdcKV4JyFEKedZxKwua/dXPUSeETGcpn0P/6BQWJzl/PGVk43C Go55bbIkBDK/lLVMHqQA81VzYo2bsXeH9PwJ93+/lcDNvykYKfZWIbUvbkDS7Y1pQVumE66CM/i qPmzleGvfaBm84UlxIi24BW0V3/jpDsemgyEn9Fj5mDV0PeDW0hDTmxcVLEjzY8w+ZA8MiuU/Kj SPWV/zds9UuAISjxKFQ== X-Proofpoint-GUID: 9H86gC-ctQrEnOK93cohHV6NZMDsegaG X-Proofpoint-ORIG-GUID: 9H86gC-ctQrEnOK93cohHV6NZMDsegaG X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDE1MCBTYWx0ZWRfX+eIyospvo4v6 bPgQtXHwmuC+FEkCQZD/OkQc9yS0XRWbSdKi0Tb75s/HEMwrc0iitoQDQ7XVURddt1+vZsWEFOj ge6xfOnxWg6uNGN6b+Ubc2yuk5qN72c= X-Authority-Analysis: v=2.4 cv=XrVvqlF9 c=1 sm=1 tr=0 ts=6ab257ee cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=M-_d4yFJWzV0JcTPBo4A:9 a=CjuIK1q_8ugA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=IRUrt_SQlIu20UJnvt05:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_07,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220150 On Tue, Sep 22, 2026 at 06:14:09PM +0800, Jie Gan wrote: > > On 9/22/2026 6:08 PM, Shawn Guo wrote: > > From: Jie Gan > > > > Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM, > > TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF > > sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace > > sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3 > > clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs, > > plus the DDR0-3 channel and LLCC TPDMs, all funneled through the > > tn_ag aggregator into the main CoreSight funnel and out to the AOSS > > sink. > > > > Signed-off-by: Jie Gan > > Signed-off-by: Shawn Guo > > --- > > arch/arm64/boot/dts/qcom/nord.dtsi | 3540 ++++++++++++++++++++++++++-- > > 1 file changed, 3314 insertions(+), 226 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi > > index 926ccf3bbe4e..3e4fbacc2eb3 100644 > > --- a/arch/arm64/boot/dts/qcom/nord.dtsi > > +++ b/arch/arm64/boot/dts/qcom/nord.dtsi > > @@ -345,6 +345,18 @@ domain_ss3: domain-sleep-0 { > > }; > > }; > > + eud-sink { > > + compatible = "arm,coresight-dummy-sink"; > > + > > + in-ports { > > + port { > > + eud_in: endpoint { > > + remote-endpoint = <&aoss_rep0_out1>; > > + }; > > + }; > > + }; > > + }; > > + > > firmware: firmware { > > scm { > > compatible = "qcom,scm-nord", > > @@ -372,6 +384,20 @@ cpu_perf: protocol@13 { > > }; > > }; > > + hpass-stm { > > + compatible = "arm,coresight-dummy-source"; > > + label = "hpass_stm"; > > + arm,static-trace-id = <25>; > > + > > + out-ports { > > + port { > > + lpass_stm_out: endpoint { > > + remote-endpoint = <&lpass_tn_in18>; > > + }; > > + }; > > + }; > > + }; > > + > > memory@80000000 { > > device_type = "memory"; > > /* Size will be updated by bootloader */ > > @@ -1900,236 +1926,3178 @@ tlmm: pinctrl@f100000 { > > wakeup-parent = <&pdc>; > > }; > > - apps_smmu_0: iommu@15a00000 { > > Hi Shawn, > > Thanks for helping post. > > This irrelevant patch diff can be avoided with git config: > git config diff.algorithm histogram. > > As Coresight patch is large, better patch diff format helps review much > easier. Ah, thanks for the tip, Jie! Just set git config up as suggested. The diff will look cleaner for the future versions. Shawn