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Fri, 25 Sep 2026 03:18:22 -0700 (PDT) Date: Fri, 25 Sep 2026 12:18:21 +0200 From: Lorenzo Bianconi To: Mohd Ayaan Anwar Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Serge Semin , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Shawn Guo , Zhangfei Gao , Jitendra Vegiraju Subject: Re: [PATCH RFC net-next 3/9] net: pcs: xpcs: add custom platform register accessors Message-ID: References: <20260923-qcom_xpcs_nord_emac-v1-0-4b1c682af70f@oss.qualcomm.com> <20260923-qcom_xpcs_nord_emac-v1-3-4b1c682af70f@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="+RQ9w07xn/7cmLLc" Content-Disposition: inline In-Reply-To: <20260923-qcom_xpcs_nord_emac-v1-3-4b1c682af70f@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=Wrq+otfv c=1 sm=1 tr=0 ts=6ab64a71 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=WpTaRW6qxYHRGzLzQsVYzg==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=cNto7lqNzDuyVZoFmAcA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 a=CjuIK1q_8ugA:10 a=TGcz8d0ICyKSqoSmTxMA:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: OXRjZ12IJC0AmSH0-2yHSr2M4ub7CGMJ X-Proofpoint-GUID: OXRjZ12IJC0AmSH0-2yHSr2M4ub7CGMJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA0MCBTYWx0ZWRfX+idS5oEYd0j2 hf3pRcf7IXMD2xomIfbyFxKciVIwdRAnwO1cDdokjzT1aX/Wi7nrl55fwX15aUQnF2aguP1J21/ iln68zzopuNrew0tNPfrk+AJ3iFbz+AIxspHk7gX9pS++8fWQenMfgbZIAmGsTVhYGfQUpLHxHf CHYD5aOeFJ9Cs+pfg65tXI09USja1oXLJY2VDm9lUz6NHcgdqexsT/UjvehvkpZQO0PWHmB8hnD IZ+GaUBv0R3FOBXeqWi+FaSfkUPnB8KWCARZWihwpNYe6r30teQz0+iimM+9OEZSpLkG5IWsTre e4kJ1Yvu49J4OSQQox7dBkjbZVz2OKTJrUm29DjOmrvq5Lk8hXmr92G3kiN1jhcDkF3OwTj9EI9 BZJxlPf7YhLLATkHjMA/70P0V5PSdiREoUHiPQ7jEBSqReTFZZq5tjnVr5JMw3wRzqNadyAPT+7 yN0xldUz8PJtmiOQ93A== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA0MCBTYWx0ZWRfX6y2RtbreyzQY LmO+f7b9QeCbKR1omSbKNmqrAX9mxS/kdEFkquwCBoGfHFQ3hhPqNFI3lLIXCEjxJV49TNrO+Ju cJ7TndLhJJkOa8iFBuHmxWxZ0UkgfH4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250040 --+RQ9w07xn/7cmLLc Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > Some XPCS integrations do not expose the standard direct or indirect > register layout. Allow the platform driver to use optional register read > and write callbacks for both Clause 22 and Clause 45 accesses, while > retaining the existing access paths when no callbacks are supplied. >=20 > Signed-off-by: Mohd Ayaan Anwar > --- > drivers/net/pcs/pcs-xpcs-plat.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) >=20 > diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-p= lat.c > index e669a7b248ac4677aeb5cd1874108f5c87f837d2..e78a233fb198d940951064a71= e8597c6c666bc9d 100644 > --- a/drivers/net/pcs/pcs-xpcs-plat.c > +++ b/drivers/net/pcs/pcs-xpcs-plat.c > @@ -24,8 +24,16 @@ > /* Page select register for the indirect MMIO CSRs access */ > #define DW_VR_CSR_VIEWPORT 0xff > =20 > +struct dw_xpcs_plat_ops { > + int (*reg_read)(struct platform_device *pdev, void __iomem *reg_base, > + int dev, int reg); > + int (*reg_write)(struct platform_device *pdev, void __iomem *reg_base, > + int dev, int reg, u16 val); I guess here we can use the same signature used in xpcs_mmio_read_reg_{direct,indirect}()/xpcs_mmio_write_reg_{direct,indirect= }(). Doing so we can probably have a generic platform ops the driver can set dur= ing probe. What do you think? Regards, Lorenzo > +}; > + > struct dw_xpcs_plat { > struct platform_device *pdev; > + const struct dw_xpcs_plat_ops *ops; > struct mii_bus *bus; > bool reg_indir; > int reg_width; > @@ -169,6 +177,10 @@ static int xpcs_mmio_read_c22(struct mii_bus *bus, i= nt addr, int reg) > if (addr !=3D 0) > return -ENODEV; > =20 > + if (pxpcs->ops) > + return pxpcs->ops->reg_read(pxpcs->pdev, pxpcs->reg_base, > + MDIO_MMD_VEND2, reg); > + > if (pxpcs->reg_indir) > return xpcs_mmio_read_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg); > else > @@ -182,6 +194,10 @@ static int xpcs_mmio_write_c22(struct mii_bus *bus, = int addr, int reg, u16 val) > if (addr !=3D 0) > return -ENODEV; > =20 > + if (pxpcs->ops) > + return pxpcs->ops->reg_write(pxpcs->pdev, pxpcs->reg_base, > + MDIO_MMD_VEND2, reg, val); > + > if (pxpcs->reg_indir) > return xpcs_mmio_write_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg, val); > else > @@ -195,6 +211,10 @@ static int xpcs_mmio_read_c45(struct mii_bus *bus, i= nt addr, int dev, int reg) > if (addr !=3D 0) > return -ENODEV; > =20 > + if (pxpcs->ops) > + return pxpcs->ops->reg_read(pxpcs->pdev, pxpcs->reg_base, > + dev, reg); > + > if (pxpcs->reg_indir) > return xpcs_mmio_read_reg_indirect(pxpcs, dev, reg); > else > @@ -209,6 +229,10 @@ static int xpcs_mmio_write_c45(struct mii_bus *bus, = int addr, int dev, > if (addr !=3D 0) > return -ENODEV; > =20 > + if (pxpcs->ops) > + return pxpcs->ops->reg_write(pxpcs->pdev, pxpcs->reg_base, > + dev, reg, val); > + > if (pxpcs->reg_indir) > return xpcs_mmio_write_reg_indirect(pxpcs, dev, reg, val); > else >=20 > --=20 > 2.34.1 >=20 --+RQ9w07xn/7cmLLc Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCarZKbQAKCRA6cBh0uS2t rJ2pAP4sM6uACZtauXlAHma3Iy2D2u2SCYHtgVPuBzVAUjSMZAEAv+u2+f2JmW/b 9fEdEMskwqkblVO/hcT8oQAkaehV4QU= =N0j3 -----END PGP SIGNATURE----- --+RQ9w07xn/7cmLLc--