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Fri, 02 Oct 2026 11:30:15 -0700 (PDT) Date: Fri, 2 Oct 2026 14:30:12 -0400 From: Brian Masney To: Conor Dooley Cc: Changhuang Liang , Michael Turquette , Jerome Brunet , Stephen Boyd , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Kees Cook , "Gustavo A . R . Silva" , Richard Cochran , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng Subject: Re: [PATCH v5 00/23] Add basic clocks and resets for JHB100 SoC Message-ID: References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> <20260930-grafting-undertake-ff3e01060284@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260930-grafting-undertake-ff3e01060284@spud> User-Agent: Mutt/2.4.2 (2026-08-30) Hi Conor, On Wed, Sep 30, 2026 at 11:43:22PM +0100, Conor Dooley wrote: > FYI clock folks, > > On Wed, Sep 30, 2026 at 05:42:54AM -0700, Changhuang Liang wrote: > > The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple > > subsystems: > > > > The JHB100 SoC is divided into multiple subsystems, and basically > > each subsystem includes a CRG(Clock and Reset Generator): > > - sys0crg/sys1crg/sys2crg/ > > - per0crg/per1crg/per2crg/per3crg/ > > - voutcrg > > - vcecrg > > - gpu0crg/gpu1crg > > - cpucrg > > - usbcrg > > - host0crg/host1crg > > - pcierpcrg > > - husb0crg/husb1crg > > - husbcmncrg > > - husbd0crg/husbd1crg > > - npucrg > > > > In the current series, we will only add the following CRG: > > - sys0crg/sys1crg/sys2crg/ > > - per0crg/per1crg/per2crg/per3crg/ > > > > The remaining CRG will be implemented in future series. > > > > This series depends on the series: > > https://lore.kernel.org/all/20260806122553.182449-1-changhuang.liang@starfivetech.com/ > > and it has been tested on the StarFive JHB100 EVB-1. > > If this revision of the series is acceptable, I'd (although I'm not a > listed driver maintainer) like to send you a PR as I've done in the past > for Starfive stuff so that I can get some of these binding patches that > contain headers as part of a shared tag to be able to unblock a bunch of > the soc tree stuff. With conferences next week I understand that, with it > being -rc5, it's probably this doesn't make v7.4 but I figured it was > worth getting my intentions out there! I am going through this series now, and I have a few minor changes to the clk drivers themselves. Feel free to send a pull for the bindings and headers though. Brian