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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-145ac67c505sm7988612c88.5.2026.09.25.17.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 17:18:35 -0700 (PDT) Date: Sat, 26 Sep 2026 08:18:29 +0800 From: Shawn Guo To: Jagadeesh Kona Cc: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Taniya Das , Jagadeesh Kona , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add videocc sleep clock Message-ID: References: <20260924161152.1162301-1-shengchao.guo@oss.qualcomm.com> <20260924161152.1162301-3-shengchao.guo@oss.qualcomm.com> <0e80efa9-9377-474e-99f5-d458d81bfcde@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0e80efa9-9377-474e-99f5-d458d81bfcde@oss.qualcomm.com> X-Proofpoint-GUID: kjmQ7F23lT3Alu62dCZ8FS5Yg9xxtPJ6 X-Authority-Analysis: v=2.4 cv=YqCa1IYX c=1 sm=1 tr=0 ts=6ab70f5e cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=ztxlnROUaC2VjM3YxSgA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: kjmQ7F23lT3Alu62dCZ8FS5Yg9xxtPJ6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI2MDAwMCBTYWx0ZWRfX3XZ5u95eGlfq L3e/6hilkgyNjz0B6NeiW11s9k6swK1reZBYo1iFyo2nkLeuHrr65PlvTYhnwSEO59R+LC/P0MS d8fTbkdmRrAiusH9kPAJDyVcLon6eDERdI38QUSyKeOgxKhUp/TmH/st7oUNrObGlFDgGEWC6Hb hpQRky59dcufwSVFEvQf//1c4m86d9M7oa+X5pBTJiXZRDc7QiEhcS9xY/jy6A7GkZAFvXHRA3K arwKOCCotIxDW5SqrSBAj2T+pNuydN7wacUk9uHL0MPvrL5t5uLJts38293VNIyUeubz78IkPK/ /FuUX82FG3D8eJfctc6EaJo0J7zhTuYEAeaF3E/1JrKEFXuZu4EpWj2HnFhXfkg6cs0fFgG9n93 rpY8SEdbwhOfIv93yALjEjs7Fex0nXNvipdrUl3WPmcwT7ECUnnBbeTqB3buiJuk22MJW7sjE9B AGnOxlmHn6mde/PRgMw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI2MDAwMCBTYWx0ZWRfXyRUrwLQb4eNI vmbOayun8SedN/ZNYcw3wV68R76Lph+zGH7BJvXG4fSZaQH33Zdiqjuv5InkJEQJi7sntLBQiSQ zZtk0L5MiIdZvqpYoU0EeYbrpu4hX2M= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609260000 On Fri, Sep 25, 2026 at 09:19:49PM +0530, Jagadeesh Kona wrote: > > On 9/24/2026 9:41 PM, Shawn Guo wrote: > > The videocc node supplies only the two XO inputs. videocc-glymur.c > > expects a third input, DT_SLEEP_CLK, and uses it as the parent of > > video_cc_sleep_clk_src, so that RCG cannot resolve its parent and ends > > up as an orphan clock: any clk_set_rate() on it fails, and it shows up > > parentless in /sys/kernel/debug/clk/clk_summary. > > > > Nothing is broken at runtime today because VIDEO_CC_SLEEP_CLK (0x8138) > > is listed in video_cc_glymur_critical_cbcrs and is therefore force > > enabled through regmap, bypassing the clock framework; the sleep source > > simply keeps whatever rate the bootloader left. The orphan still blocks > > any future rate management of the video sleep path. > > > > Hi Shawn, > > The sleep clock supports only a fixed 32KHz frequency and does not support > any other frequencies. Additionally, this clock is not currently used or voted > on by any consumers. Therefore, leaving it in its default bootloader configured > rate should be sufficient, and this change isn't really required. Hi Jagadeesh, Agreed on both facts, and the commit message says as much: nothing is broken at runtime and there is no rate to manage. The patch is not about fixing a functional failure though, it is about the DT describing the hardware inputs the block actually has. video_cc_sleep_clk_src's parent_map contains P_SLEEP_CLK and its freq_tbl has F(32000, P_SLEEP_CLK, 1, 0, 0), so the RCG really does take a sleep clock input in hardware, and videocc-glymur.c asks the DT for it via DT_SLEEP_CLK. A DT that stops at two inputs leaves that input undescribed regardless of whether anyone votes on it today. It also matters for the binding. The schema currently documents two inputs for every compatible, which is wrong for qcom,glymur-videocc, and I am fixing that in the preceding patch of this series. If the DTS keeps only two entries it no longer matches its own binding. Shawn