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From: "Luck, Tony" <tony.luck@intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: "Drew Fustini" <fustini@kernel.org>,
	"Adrien Ricciardi" <aricciardi@baylibre.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Babu Moger" <babu.moger@amd.com>,
	"Ben Horgan" <ben.horgan@arm.com>,
	"Borislav Petkov" <bp@alien8.de>,
	"Chen Pei" <cp0613@linux.alibaba.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	"Dave Martin" <Dave.Martin@arm.com>,
	"Fenghua Yu" <fenghuay@nvidia.com>,
	"Gong Shuai" <gong.shuai@sanechips.com.cn>,
	"Gong Shuai" <gsh517@gmail.com>,
	guo.wenjia23@zte.com.cn, "James Morse" <james.morse@arm.com>,
	"Kornel Dulęba" <mindal@semihalf.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	liu.qingtao2@zte.com.cn,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <pjw@kernel.org>,
	"Peter Newman" <peternewman@google.com>,
	"Radim Krčmář" <rkrcmar@ventanamicro.com>,
	"Rob Herring" <robh@kernel.org>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
	"Vasudevan Srinivasan" <vasu@rivosinc.com>,
	"Ved Shanbhogue" <ved@rivosinc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"yunhui cui" <cuiyunhui@bytedance.com>,
	"Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	x86@kernel.org, devicetree@vger.kernel.org,
	linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org
Subject: Re: [PATCH v7 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask
Date: Mon, 12 Oct 2026 10:31:38 -0700	[thread overview]
Message-ID: <as0Zeoyjiy5CW1DT@agluck-desk3> (raw)
In-Reply-To: <aqwN1szItGPg4Qjh@agluck-desk3>

On Thu, Sep 17, 2026 at 08:57:10AM -0700, Luck, Tony wrote:
> On Thu, Sep 17, 2026 at 08:37:43AM -0700, Reinette Chatre wrote:
> > Hi Drew,
> > 
> > On 9/1/26 3:31 PM, Drew Fustini wrote:
> > > resctrl exposes a single cap set per rid, so when more than one capacity
> > > controller backs a cache level they must agree on those caps. A level
> > > whose controllers disagree is left unexposed. Other levels are
> > > unaffected.
> > If I understand correctly, while attempting to translate to resctrl terms,
> > this means that a cache resource with several domains may support different
> > capacity masks in the domains?
> > 
> > I believe the "single cap set per rid" you refer to is
> > /sys/fs/resctrl/info/L3/cbm_mask and /sys/fs/resctrl/info/L2/cbm_mask that
> > exposes a single capacity bitmask representing the maximum allocation.
> > 
> > As you know, resctrl is in the process of changing the way in which schema
> > formats are described. The most recent PoC [1] added new bitmap description
> > files but it kept a single value "max" file to describe the highest allocation
> > possible for a bitmap schema.
> > 
> > To support asymmetrical cache instances it looks like changing the interface
> > to describe the maximum per domain (instead of one global value) could address
> > the gap?
> > 
> > For example, if there is a hypothetical system with two L2 cache instances, one
> > with a 0xFF max CBM and the other with a 0XF max CBM then resctrl could expose it
> > as:
> 
> That sounds like the not-at-all-hypothetical Intel hybrid client parts
> where P-core and E-core have different L2 masks.
> 
> > 
> > 	# cat /sys/fs/resctrl/info/L2/schemata/L2/max
> > 	0=ff;1=f
> > 
> > The schemata file currently and will continue to display the allocations per domain.
> > 
> > resctrl will need more changes to support different CBM per domain internally and
> > until then all these CBMs will be the same, but adding this change to user interface now
> > may set resctrl up to support these systems in the future?
> 
> I think Fenghua once worked on patches to support this. But I don't
> think they were every posted to LKML. One of the open issues at the time
> was how to handle the info/L2/cbm_mask file.

I took git://git.kernel.org/pub/scm/linux/kernel/git/reinette/linux.git
branch resctrl/controls_rfc_v2.4 and added some patches to support L2
per-domain cache allocation bitmasks. Seems to be working OK. I can
share the patches if anyone is interested, but they aren't even up to
RFC quality yet.

I do have some questions:

1) The repeated "L2" in the path seems awkward. The first is the
resource name, the second the control name. Makes sense for MBA where
there may be multiple control names. But for cache ... is there a better
name for the control than repeating the resource name?

2) Should the format of /sys/fs/resctrl/info/L2/schemata/L2/max depend
on whether the platform is asymmetric? Or just enumerate the per-domain
values even on symmetric systems? Likely easier for users to list all
domains.

3) What should happen to the legacy /sys/fs/resctrl/info/L2/cbm_mask?
Just hide it? I also considered renaming the resource to "L2A" to
avoid surprising legacy code.

-Tony

  reply	other threads:[~2026-10-12 17:31 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-01 22:31 [PATCH v7 0/5] riscv: Add Ssqosid and initial CBQRI resctrl support Drew Fustini
2026-09-01 22:31 ` [PATCH v7 1/5] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-09-01 22:42   ` sashiko-bot
2026-09-01 22:31 ` [PATCH v7 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-09-17 15:37   ` Reinette Chatre
2026-09-17 15:57     ` Luck, Tony
2026-10-12 17:31       ` Luck, Tony [this message]
2026-10-13  0:07         ` Reinette Chatre
2026-10-13 15:55           ` Luck, Tony
2026-10-13 17:42             ` Reinette Chatre
2026-09-17 16:18     ` Drew Fustini
2026-09-17 16:27       ` Reinette Chatre
2026-09-01 22:31 ` [PATCH v7 3/5] riscv: Enable resctrl filesystem for Ssqosid Drew Fustini
2026-09-01 22:31 ` [PATCH v7 4/5] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-09-01 22:31 ` [PATCH v7 5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini
2026-09-03  3:24 ` [PATCH v7 0/5] riscv: Add Ssqosid and initial CBQRI resctrl support Chen Pei

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