Re: [PATCH v3 2/6] clk: qcom: negcc-nord: keep GPU2 CFG clock enabled via critical CBCR

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Fri, Jul 24, 2026 at 04:25:06PM +0530, Taniya Das wrote:
> The GPU2 CFG clock must remain enabled for correct operation and
> should not be exposed as a controllable clk_branch.

Hi Taniya,

Could you share a bit more information why this is the case? I do not
seem to get any problem when testing without this change.

Shawn

> 
> Remove the clk_branch and mark its CBCR as critical instead to
> prevent unintended gating. This follows the same approach as
> 'nw_gcc_gpu_cfg_ahb_clk' and aligns with other always-on clocks in
> Qualcomm CC drivers.
> 
> Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/negcc-nord.c | 22 ++++++----------------
>  1 file changed, 6 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c
> index 2e653ef0fe0e304f09ed354d5578fdbed9151d20..bc4d478d5606ad7478431573f98b62f6f9b7d9fb 100644
> --- a/drivers/clk/qcom/negcc-nord.c
> +++ b/drivers/clk/qcom/negcc-nord.c
> @@ -952,21 +952,6 @@ static struct clk_branch ne_gcc_gp2_clk = {
>  	},
>  };
>  
> -static struct clk_branch ne_gcc_gpu_2_cfg_clk = {
> -	.halt_reg = 0x34004,
> -	.halt_check = BRANCH_HALT_VOTED,
> -	.hwcg_reg = 0x34004,
> -	.hwcg_bit = 1,
> -	.clkr = {
> -		.enable_reg = 0x34004,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "ne_gcc_gpu_2_cfg_clk",
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = {
>  	.halt_check = BRANCH_HALT_DELAY,
>  	.clkr = {
> @@ -1817,7 +1802,6 @@ static struct clk_regmap *ne_gcc_nord_clocks[] = {
>  	[NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr,
>  	[NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr,
>  	[NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr,
> -	[NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr,
>  	[NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr,
>  	[NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr,
>  	[NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr,
> @@ -1946,10 +1930,16 @@ static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
>  	qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
>  }
>  
> +static const u32 ne_gcc_nord_critical_cbcrs[] = {
> +	0x34004, /* NE_GCC_GPU_2_CFG_CLK */
> +};
> +
>  static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
>  	.dfs_rcgs = ne_gcc_nord_dfs_clocks,
>  	.num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
>  	.clk_regs_configure = clk_nord_regs_configure,
> +	.clk_cbcrs = ne_gcc_nord_critical_cbcrs,
> +	.num_clk_cbcrs = ARRAY_SIZE(ne_gcc_nord_critical_cbcrs),
>  };
>  
>  static const struct qcom_cc_desc ne_gcc_nord_desc = {
> 
> -- 
> 2.34.1
> 
>