From: Thierry Reding <thierry.reding@kernel.org>
To: Sasha Levin <sashal@kernel.org>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Lyude Paul <lyude@redhat.com>,
Danilo Krummrich <dakr@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Alexandre Courbot <acourbot@nvidia.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
Aaron Kling <webgeek1234@gmail.com>,
Dmitry Osipenko <dmitry.osipenko@collabora.com>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered
Date: Tue, 13 Oct 2026 17:44:34 +0200 [thread overview]
Message-ID: <as5Q_Ukc9Ivzpzg0@orome> (raw)
In-Reply-To: <20261013145210.103565-3-sashal@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 2456 bytes --]
On Tue, Oct 13, 2026 at 10:52:10AM -0400, Sasha Levin wrote:
> Since the GPU on the Jetson TX1 was enabled in commit d1b725476104
> ("arm64: tegra: p2180: Explicitly enable GPU"), nouveau often fails to
> bring up the GM20B. Either BOOT_0 reads back garbage ("unknown chipset
> (5ffefa47)"), or PRI reads of the GPC PLL time out ("MMIO read of
> 00000000 FAULT at 137000 [ TIMEOUT ]"), or the first register reads in
> nvkm_device_ctor() stall until an asynchronous SError. How often depends
> on the board; one board fails on every boot.
>
> nouveau powers the GPU up with the fuse clock gated: since commit
> 24a15252ff04 ("soc/tegra: fuse: Add runtime PM support"), the Tegra fuse
> driver only enables that clock around its own fuse reads. NVIDIA's
> downstream nvgpu driver enables the fuse clock along with the other GPU
> clocks whenever the GPU is powered. Do the same: take an optional "fuse"
> clock and keep it enabled from before the GPU rail is turned on until
> after it is turned off.
>
> Tested on eight Jetson TX1 devkits, on mainline and on v6.18. Without
> this patch, the GPU failed to come up in 27 of 109 boots; with it, in 11
> of 291, none of them with a garbage BOOT_0. On the board that failed on
> every boot, 38 of 40 boots now succeed. The remaining failures are
> mostly a register read that stalls until an SError; wherever the console
> shows when, nouveau had already finished probing. Such stalls also occur
> without this patch and are a separate problem. The Jetson Nano, which
> shares the Tegra210 GPU node, still works (24 of 24 boots).
>
> Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
> drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h | 1 +
> drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
Given the failure rates, I'm almost tempted to say we need to break DT
ABI and consider the FUSE clock to be required, in which case the driver
should use the regular devm_clk_get() instead of the optional variant.
As you said, we probably got away with this for a long time because we
either didn't enabled the GPU by default or because the FUSE clock was
always turned on. Or we might've tested GPU as built-in, in which case
the FUSE clock might have still been on (not disabled after early boot
yet).
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2026-10-13 15:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 14:52 [PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock Sasha Levin
2026-10-13 14:52 ` [PATCH 2/3] arm64: tegra: Add the fuse clock to the Tegra210 GPU Sasha Levin
2026-10-13 15:37 ` Thierry Reding
2026-10-13 14:52 ` [PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered Sasha Levin
2026-10-13 14:58 ` sashiko-bot
2026-10-13 15:44 ` Thierry Reding [this message]
2026-10-13 15:36 ` [PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock Thierry Reding
2026-10-13 15:46 ` Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=as5Q_Ukc9Ivzpzg0@orome \
--to=thierry.reding@kernel.org \
--cc=acourbot@nvidia.com \
--cc=airlied@gmail.com \
--cc=conor+dt@kernel.org \
--cc=dakr@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.osipenko@collabora.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=jonathanh@nvidia.com \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lyude@redhat.com \
--cc=maarten.lankhorst@linux.intel.com \
--cc=mperttunen@nvidia.com \
--cc=mripard@kernel.org \
--cc=nouveau@lists.freedesktop.org \
--cc=robh@kernel.org \
--cc=sashal@kernel.org \
--cc=simona@ffwll.ch \
--cc=tzimmermann@suse.de \
--cc=webgeek1234@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox