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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537cb68e56sm17840817eec.29.2026.10.10.20.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2026 20:25:23 -0700 (PDT) Date: Sun, 11 Oct 2026 11:25:15 +0800 From: Shawn Guo To: Akhil P Oommen Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Abel Vesa , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Shivam Rawat Subject: Re: [PATCH 3/5] arm64: dts: qcom: nord: Add Adreno 753 GPU and GMU nodes Message-ID: References: <20261009-nord-gpu1-v1-0-a06a6c57bde7@oss.qualcomm.com> <20261009-nord-gpu1-v1-3-a06a6c57bde7@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261009-nord-gpu1-v1-3-a06a6c57bde7@oss.qualcomm.com> X-Proofpoint-ORIG-GUID: Wc2genIYg4uFhYfrWJdcBgc0HqCi8E8p X-Proofpoint-GUID: Wc2genIYg4uFhYfrWJdcBgc0HqCi8E8p X-Authority-Analysis: v=2.4 cv=E6hYNqdl c=1 sm=1 tr=0 ts=6acb01a5 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=BJWcozxxeopv1PEHIoIA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDExMDAxMyBTYWx0ZWRfX5LsoUgkeQ73D oFaM7HFJq3gxAtfFN87I4622xxlnzku0yctgNsYFIxmv7kNinQEJDe+CQtKQRk/CwjF7+WG91d3 zYfG95yed5scg5/Nbrmaa2rvDnqomkKTu2gmQyr00IcNaLJlSDVKNgfIZkGubuyzW8t3w2Z6+ue cTvAFijp+Z1FtNthsqWoYqZI9oABBBtfynOzMPx5+39YVnslw0OCUXcdAoPWauxJ3Y7rg57xwun G5nJ9WgTkv4jZc9t9KRbv88/763jL/h4f2kAqSPiTCqwIUlipfHA1LcMPdQ9fVBvA9FSBGI8Dsh EVtN55Fly4vMjPGeAw3v/Vm0lfXzmzV/Ba/q5xSmQ9rIwG+OisvbA1BeQYdJJPW331zbrM4Pm46 1tLHHwkF1pPcqEPpR0VJYuIGT9AxtsMFWEQy+hjgkJk3oQUDnCPwaHVRSHIk48Kas74ksP0ZDiY Y291akcOlaHQBQFRkbw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDExMDAxMyBTYWx0ZWRfX5V8chiSYc2NA Z7YnFeecUCbIyaTxzYCPJKGW80Dks5KJU9fsZsHVb7jhcUClijX6hlwsbnEoGPH6Q5b9dznWxtx HkcUpHfFnK5Im/9VPt2DIIoVFpYtv4M= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-11_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610110013 On Fri, Oct 09, 2026 at 02:36:37AM +0530, Akhil P Oommen wrote: > From: Shivam Rawat > > Nord SoC integrates an Adreno 753 GPU as its primary GPU, belonging to > the A7xx Gen3 family, along with its Graphics Management Unit (GMU). > > Add the GPU and GMU nodes together with their OPP tables. The GPU sits > behind adreno_smmu_0 and uses the gen71300 zap shader, while the GMU is > clocked and powered from GPUCC. > > Unlike previous Adreno SoCs, where the GMU AXI clock comes from the > single global clock controller, Nord splits its GCC into four blocks > (GCC, SE_GCC, NE_GCC and NW_GCC). The GPU's AXI clock, > NW_GCC_HSCNOC_GPU_AXI_CLK, is provided by NW_GCC, so the GMU node > references nwgcc directly. > > Signed-off-by: Shivam Rawat > Signed-off-by: Akhil P Oommen > --- > arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 116 ++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi > index 1ab7d9bc3cfe..4379092b7bf8 100644 > --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi > +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi > @@ -776,6 +776,122 @@ hscnoc: interconnect@2000000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + gpu_0: gpu@3d00000 { > + compatible = "qcom,adreno-43051701", "qcom,adreno"; > + reg = <0x0 0x03d00000 0x0 0x40000>, > + <0x0 0x03d9e000 0x0 0x2000>, > + <0x0 0x03d61000 0x0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", > + "cx_mem", > + "cx_dbgc"; nord-embedded.dtsi is created to accommodate Nord Embedded (Non-GearVM) variant specific resources like clocks, resets, power dmains, interconects, PHYs, etc. The common resources like reg, interrupts, iommus, etc, should go to nord.dts. Please follow the existing device examples to do the split. Shawn > + > + interrupts = ; > + > + iommus = <&adreno_smmu_0 0 0x0>, > + <&adreno_smmu_0 1 0x0>; > + > + operating-points-v2 = <&gpu_opp_table_0>; > + > + qcom,gmu = <&gmu_0>; > + #cooling-cells = <2>; > + > + interconnects = <&hscnoc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "gfx-mem"; > + > + status = "disabled"; > + > + gpu_0_zap_shader: zap-shader { > + memory-region = <&gpu_microcode_mem>; > + }; > + > + gpu_opp_table_0: opp-table { > + compatible = "operating-points-v2-adreno", > + "operating-points-v2"; > + > + opp-468000000 { > + opp-hz = /bits/ 64 <468000000>; > + opp-level = ; > + opp-peak-kBps = <781250>; > + }; > + > + opp-625000000 { > + opp-hz = /bits/ 64 <625000000>; > + opp-level = ; > + opp-peak-kBps = <6075000>; > + }; > + > + opp-735000000 { > + opp-hz = /bits/ 64 <735000000>; > + opp-level = ; > + opp-peak-kBps = <8175000>; > + }; > + > + opp-854000000 { > + opp-hz = /bits/ 64 <854000000>; > + opp-level = ; > + opp-peak-kBps = <10687500>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-level = ; > + opp-peak-kBps = <12450000>; > + }; > + }; > + }; > + > + gmu_0: gmu@3d6a000 { > + compatible = "qcom,adreno-gmu-753.1", "qcom,adreno-gmu"; > + reg = <0x0 0x03d6a000 0x0 0x35000>, > + <0x0 0x03d50000 0x0 0x10000>, > + <0x0 0x0b2a0000 0x0 0x10000>; > + reg-names = "gmu", > + "rscc", > + "gmu_pdc"; > + > + interrupts = , > + ; > + interrupt-names = "hfi", > + "gmu"; > + > + clocks = <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&nwgcc NW_GCC_HSCNOC_GPU_AXI_CLK>, > + <&gpucc GPU_CC_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>; > + clock-names = "ahb", > + "gmu", > + "cxo", > + "axi", > + "memnoc", > + "hub"; > + > + power-domains = <&gpucc GPU_CC_CX_GDSC>, > + <&gpucc GPU_CC_GX_GDSC>; > + power-domain-names = "cx", > + "gx"; > + > + iommus = <&adreno_smmu_0 5 0x0>; > + > + operating-points-v2 = <&gmu_opp_table_0>; > + > + gmu_opp_table_0: opp-table { > + compatible = "operating-points-v2"; > + > + opp-416666000 { > + opp-hz = /bits/ 64 <416666000>; > + opp-level = ; > + }; > + > + opp-625000000 { > + opp-hz = /bits/ 64 <625000000>; > + opp-level = ; > + }; > + }; > + }; > + > gpucc: clock-controller@3d90000 { > compatible = "qcom,nord-gpucc"; > reg = <0x0 0x03d90000 0x0 0x9800>; > > -- > 2.55.0 > >