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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-896c3ccc67asm3738084b3a.32.2026.10.11.23.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 23:37:48 -0700 (PDT) Date: Mon, 12 Oct 2026 14:37:41 +0800 From: Shawn Guo To: Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Bartosz Golaszewski Subject: Re: [PATCH v2 1/5] arm64: dts: qcom: nord: Add PCIe PHY and controller nodes Message-ID: References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> <20260915015632.283642-2-shengchao.guo@oss.qualcomm.com> <086f87b9-9b9a-4acb-b18c-be37cd6558da@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <086f87b9-9b9a-4acb-b18c-be37cd6558da@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDAyNiBTYWx0ZWRfX+ieN1n/+XPH2 TePt+HrkcfG23J4GMFse0EuNDKueajrROsS/3ierewCUARYY40/Z/8M0WLZkKFFsd+QOCJiJKmv MgEXZ3iVz8IZ9/TdhOQLQW/ls3PRbWEocks4QYXph/JtZE76NNwWIBU3gtUyb8s5l6KMgSTQNa6 LEbP+0Z7ITbzCyermGVJgq/Wwo8f8dP0a1m/4gbbtEXh8T2pidWQEKuVrgYFx4pwaJEgvGU/ztX /8O7t8JFeS+fhAbXuxXa6xvZnh9mpsK8P3bRZ1NRjkEgs7Bxrxu2/hVMAXo/e4SEXrjIN/7FdD2 utHmCht7/uDUeQqb/sUJlZtKSSDKULeHNLwjNIIyXMHi3v5VxDBm2qa1/EvrkRfcmnFfPHJByYp +mU0dvySVr7VE9QUoMqQ2nUyAo2roaOcctbMGtEYUTZswtGS09gBJ/w287gw0orj6FW7H8y90ke pVE0WX7A0W98KP2k67w== X-Proofpoint-ORIG-GUID: YbnkkX4pEdl2N2RNoVP1Ld96t9fcvt7v X-Proofpoint-GUID: YbnkkX4pEdl2N2RNoVP1Ld96t9fcvt7v X-Authority-Analysis: v=2.4 cv=W5utxhWk c=1 sm=1 tr=0 ts=6acc803d cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=v2e4zakv3qIv4HXwh4oA:9 a=CjuIK1q_8ugA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDAyNiBTYWx0ZWRfX4/j1X7N+1agJ 3nm6R9vmX1LA+XYjjnF5N48+SxOhLZpBdHSs0DtLwm4wFuAUMnyZBXhXbYMRkQcQ0Qrl5qEHcXt C9x7wNE5heAfWVikVl7RhuYx3KujizQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_02,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 phishscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120026 On Mon, Oct 12, 2026 at 10:52:34AM +0530, Krishna Chaitanya Chundru wrote: > > > On 10/10/2026 8:04 AM, Shawn Guo wrote: > > On Tue, Sep 15, 2026 at 09:56:28AM +0800, Shawn Guo wrote: > >> From: Krishna Chaitanya Chundru > >> > >> Nord has four PCIe controllers backed by a single quadfurcated Gen5 > >> QMP PHY with four ports (A/B/C/D) and a common PCIe SMMU. The ports > >> can be ganged into x16, x8+x8, x8+x4+x4 or x8+x4+x2+x2 topologies; the > >> topology in effect is selected by firmware through the TCSR link-config > >> mode register, which the PHY driver reads at probe time. Describe the > >> x8+x4+x2+x2 topology, i.e. all four controllers usable, as that is the > >> configuration the boards ship with. > >> > >> Add the controller and SMMU nodes to nord.dtsi, and the PHY node along > >> with the per-controller clocks, resets, GDSCs, interconnects, OPP tables > >> and TLMM pin states to nord-embedded.dtsi. The four PCIe pipe clocks > >> also become available now, so hook them up as GCC parents in place of > >> the <0> placeholders. > >> > >> The controllers and the PHY are left disabled here and enabled per > >> board. > >> > >> Signed-off-by: Krishna Chaitanya Chundru > >> Reviewed-by: Abel Vesa > >> Reviewed-by: Bartosz Golaszewski > >> Signed-off-by: Shawn Guo [...] > >> &tlmm { > >> + pcie0_default: pcie0-default-state { > >> + wake-pins { > >> + pins = "gpio0"; > >> + function = "gpio"; > >> + drive-strength = <2>; > >> + bias-pull-up; > >> + }; > >> + > >> + clkreq-pins { > >> + pins = "gpio1"; > >> + function = "pcie0_clk_req_n"; > >> + drive-strength = <2>; > >> + bias-pull-up; > >> + }; > >> + > >> + perst-pins { > >> + pins = "gpio2"; > >> + function = "gpio"; > >> + drive-strength = <2>; > >> + bias-disable; > >> + }; > > pcie0_clk_req_n is a SoC level pin function, so it has a good reason to > > stay here. But wake and perst are board chosen GPIOs. I think they should > > go to board DTS. > Shawn, I don't see perst and wake gpios are changing per board, for that > reason I added them here, but such requirement is coming we can move them to > board file. Well, we have only seen Ride and RRD so far. We never know how other Nord based boards to come will choose the perst and wake GPIOs. This is simply a board level configuration and should go to board dts. Shawn