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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cd3da04d46asm4175732a12.30.2026.10.12.01.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 01:59:29 -0700 (PDT) Date: Mon, 12 Oct 2026 16:59:23 +0800 From: Shawn Guo To: Konrad Dybcio Cc: Krishna Chaitanya Chundru , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Bartosz Golaszewski Subject: Re: [PATCH v2 1/5] arm64: dts: qcom: nord: Add PCIe PHY and controller nodes Message-ID: References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> <20260915015632.283642-2-shengchao.guo@oss.qualcomm.com> <086f87b9-9b9a-4acb-b18c-be37cd6558da@oss.qualcomm.com> <2ca0fff3-aadc-4dcd-93e8-df2ffbac08ab@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2ca0fff3-aadc-4dcd-93e8-df2ffbac08ab@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDAzNSBTYWx0ZWRfX0CVkoKLS07rX xBXdmEHb/KjuuFSSO1oO2lBuPlR4VcN9ZDqiGy1RDQ9ZSCpZFgaJuLEYuWIgtoDQ9yPai4oGa64 TNsoIBN372puDqonclLuqs48aDMjH34ZiapcPVuiuyhp0/Mvn9KV1o3n4H/weKYxBCzecmzWktH H1MP1lTI0CyNMam6RRM5McvyYpHfbJhC+yzM05jGftefGPZsxxZ29qKOeFQtxWlKaH3+QC4g0fn KDuybLWLguK45zYdFpzOTB6ngnQkPb6zFGy6c4erB/aAJ8qjU+KSRvLzI9ow7sIMMeL9t3iZCNh gBpHAu79wOvRuh/qoMlRdHOTMnl0KvzAIeCoDB/ndkDPTaQL2dSRtfEJ0LY2WNwrZgSZm82ki2D lwnhtkLo3Pt3sTw3p+W+HJGayfPq9pWvGGrvtRktzc1GFRqErgdZB05jBGG6WlZJEl7+etizOZS YdNQm0lCj5o/CiPlsTg== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDAzNSBTYWx0ZWRfX3QPmt8D0uBwa lj1tMrjggf4cH0O2RrXXotdTIq/huluaCkJuC4Qz++C2bGNyv4pMCeH/Ex03eZGgWDcZeoGm0j0 0Kbft18MVPy8zqYpsRlatoy+/OhfcLY= X-Authority-Analysis: v=2.4 cv=VOtIDNPX c=1 sm=1 tr=0 ts=6acca173 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=rYj7rt9JKJ1DByYstP4A:9 a=CjuIK1q_8ugA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: A_SsbEALuRRx-ey0XmfsGCQxFQ6Y-sw7 X-Proofpoint-ORIG-GUID: A_SsbEALuRRx-ey0XmfsGCQxFQ6Y-sw7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_03,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120035 On Mon, Oct 12, 2026 at 09:40:24AM +0200, Konrad Dybcio wrote: > On 10/12/26 8:37 AM, Shawn Guo wrote: > > On Mon, Oct 12, 2026 at 10:52:34AM +0530, Krishna Chaitanya Chundru wrote: > >> > >> > >> On 10/10/2026 8:04 AM, Shawn Guo wrote: > >>> On Tue, Sep 15, 2026 at 09:56:28AM +0800, Shawn Guo wrote: > >>>> From: Krishna Chaitanya Chundru > > [...] > > >>>> + perst-pins { > >>>> + pins = "gpio2"; > >>>> + function = "gpio"; > >>>> + drive-strength = <2>; > >>>> + bias-disable; > >>>> + }; > >>> pcie0_clk_req_n is a SoC level pin function, so it has a good reason to > >>> stay here. But wake and perst are board chosen GPIOs. I think they should > >>> go to board DTS. > >> Shawn, I don't see perst and wake gpios are changing per board, for that > >> reason I added them here, but such requirement is coming we can move them to > >> board file. > > > > Well, we have only seen Ride and RRD so far. We never know how other Nord > > based boards to come will choose the perst and wake GPIOs. This is > > simply a board level configuration and should go to board dts. > > They never do in practice (for a good reason, the reference-chosen pins are > consecutive and presumably next to each other) Ah, good point! That's indeed a good reason to keep PCIe perst and wake GPIO in nord-embedded.dtsi along with clk_req_n. Shawn > and we have no occurences of > that in the tree across the hundreds of devices.