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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
	linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
	Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
	linux-kernel@vger.kernel.org, Chanho Min <chanho.min@lge.com>
Subject: Re: [PATCH v10 4/8] gpio: pl061: convert register access to regmap
Date: Thu, 15 Oct 2026 22:28:54 +0300	[thread overview]
Message-ID: <atEpdoHAHouGHWYv@ashevche-desk.local> (raw)
In-Reply-To: <20261015-cv75-gpio-v10-4-3fe3eb315a55@ambarella.com>

On Thu, Oct 15, 2026 at 06:53:31PM +0800, Long Zhao via B4 Relay wrote:
> 
> Replace readb()/writeb() with a MMIO regmap while keeping the existing
> gpio_chip and girq irqchip. Use a raw spinlock so irq_ack() can run
> under the irq descriptor lock.

A few nit-picks, otherwise
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

...

> static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
>  {
>  	struct pl061 *pl061 = gpiochip_get_data(gc);
>  
> -	return !!readb(pl061->base + (BIT(offset + 2)));
> +	return regmap_test_bits(pl061->regmap,
> +				BIT(offset + PL061_DATA_OFFSET),
> +				BIT(offset));

There is some room on the previous line.

	return regmap_test_bits(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
				BIT(offset));

>  }

...

>  static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int value)
>  {
>  	struct pl061 *pl061 = gpiochip_get_data(gc);
>  
> -	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
> +	regmap_assign_bits(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
> +			   BIT(offset), value);
>  
>  	return 0;

Can we actually return the regmap_assign_bits() error code here?

>  }

...

> static int pl061_irq_type(struct irq_data *d, unsigned trigger)

>  	struct pl061 *pl061 = gpiochip_get_data(gc);
>  	int offset = irqd_to_hwirq(d);
>  	unsigned long flags;
> -	u8 gpiois, gpioibe, gpioiev;
> -	u8 bit = BIT(offset);
> +	unsigned int gpioiev = 0;
> +	unsigned int gpioibe = 0;
> +	unsigned int gpiois = 0;
> +	unsigned int bit = BIT(offset);

Keep the reversed xmas tree order.

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2026-10-15 19:29 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-15 10:53 [PATCH v10 0/8] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-15 10:53 ` [PATCH v10 1/8] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-15 10:53 ` [PATCH v10 2/8] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-15 11:01   ` sashiko-bot
2026-10-15 10:53 ` [PATCH v10 3/8] gpio: pl061: drop redundant pending check in the IRQ handler Long Zhao via B4 Relay
2026-10-15 19:21   ` Andy Shevchenko
2026-10-15 10:53 ` [PATCH v10 4/8] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-15 19:28   ` Andy Shevchenko [this message]
2026-10-15 10:53 ` [PATCH v10 5/8] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-15 10:53 ` [PATCH v10 6/8] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-15 19:31   ` Andy Shevchenko
2026-10-15 10:53 ` [PATCH v10 7/8] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-15 11:04   ` sashiko-bot
2026-10-15 19:48   ` Andy Shevchenko
2026-10-15 10:53 ` [PATCH v10 8/8] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-10-15 11:08   ` sashiko-bot

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