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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-360813b63e1sm8146987eec.8.2026.10.16.06.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 06:52:59 -0700 (PDT) Date: Fri, 16 Oct 2026 21:52:52 +0800 From: Shawn Guo To: Mohammad Rafi Shaik Cc: Shenghao Ding , Kevin Lu , Baojun Xu , Sen Wang , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Srinivas Kandagatla , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v3 2/7] ASoC: codec: pcm1681: Add optional SCK clock and runtime PM support Message-ID: References: <20261009-nord-asoc-driver-support-v3-v3-0-0c1897f21ccf@oss.qualcomm.com> <20261009-nord-asoc-driver-support-v3-v3-2-0c1897f21ccf@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20261009-nord-asoc-driver-support-v3-v3-2-0c1897f21ccf@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDA1NSBTYWx0ZWRfX+F7ZTUTK90f/ oVspIQlkfejZiFOhttmFU65qaNXZ5zXCjWPAn5tIBE7fdZXeVLPqlAPHIFb71bJsVSxDVEJCGYU bKZD7I9MfQBVvhaZruVGaaN6Qi3s5BtN5wNql3kKa+ewUB47tXF+EIlkdr9e0gaB6Ex2v50jlvS PJJinWMoTtMBeD0Te9ntBS/3FKwKWZ9w+EoFdiV8P7F/Ujv2NTTnglX48JjWsJFKjZAVbNxfQqQ U7uRusLcWY+XbNiGhSzGB1zreqFfKlk8yAwMIhRTyw4WFFeS/KokE3lv433d66AE4hWVTwi7Tu6 wxaLhnUnWe5NyA9E6ySZmkhcaUy+76jxTxSvUj0XCm2n6ivAxfigCovgUsW1aPrhyqlGCwFDyYi 5c/XqAZ6MBd+VqR2dXspe6c0MYU7iZekKazZRPImHMFGQd4cpvoCnudPD7tnL8QuRO2G8A/1iY4 CTzHIn7xhnM1It+NQgQ== X-Proofpoint-ORIG-GUID: UIxkDGg2VMLdKlwll0dQeb97TQEZKiAk X-Proofpoint-GUID: UIxkDGg2VMLdKlwll0dQeb97TQEZKiAk X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDA1NSBTYWx0ZWRfX5GhUoq4eDLya cQlT4yJVslJF0/zO7wwePN5aXsXvdiKRECmLN5Yl/7d9uEHzpHV/5UWDTohQvV6Uf878UWOqpFy p1lWEvlhvB0VAMZKfgoRnFwq0fYkdoM= X-Authority-Analysis: v=2.4 cv=VpS2kO2n c=1 sm=1 tr=0 ts=6ad22c3d cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=8nJEP1OIZ-IA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=hIk10_Rze-2l0Qr3NckA:9 a=3ZKOabzyN94A:10 a=wPNLvfGTeEIA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-16_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160055 On Fri, Oct 09, 2026 at 06:42:48PM +0530, Mohammad Rafi Shaik wrote: > The PCM1681 requires its SCK system clock to be running before register > access. On platforms where SCK is provided by a gateable clock, register > access may fail when the clock is disabled. >   > Add support for an optional "sck" clock and enable it before accessing the > device. After enabling SCK, wait for the required 65536 system clock cycles > to allow the device to complete its internal reset sequence. >   > Use runtime PM to manage SCK instead of keeping it enabled for the lifetime > of the device. Disable the clock during runtime suspend and restore it on > runtime resume. Use autosuspend to avoid unnecessary clock toggling between > closely spaced accesses. >   > Since the device register state may be lost when SCK is disabled, enable > the regmap cache. Switch regmap to cache-only mode and mark the cache > dirty on runtime suspend, then synchronize the cached register state after > SCK is restored on runtime resume. Mark the zero-detect status register > volatile since it is updated by hardware. >   > Drop idle_bias_on so that the component can reach SND_SOC_BIAS_OFF and > runtime suspend can gate SCK. > > Assisted-by: LLM > Signed-off-by: Mohammad Rafi Shaik [...] > @@ -304,34 +335,128 @@ MODULE_DEVICE_TABLE(i2c, pcm1681_i2c_id); > > static int pcm1681_i2c_probe(struct i2c_client *client) > { > + struct device *dev = &client->dev; > int ret; > struct pcm1681_private *priv; > > - priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > if (!priv) > return -ENOMEM; > > + priv->sck = devm_clk_get_optional(dev, "sck"); > + if (IS_ERR(priv->sck)) > + return dev_err_probe(dev, PTR_ERR(priv->sck), > + "Failed to get sck\n"); Holding sck from i2c probe for the lifetime of the device breaks audio after an ADSP restart on Nord. There sck is LPASS_CLK_ID_MCLK_1 from q6prmcc, a clock controller that lives under the ADSP GPR service. Stopping the ADSP removes q6prm and unregisters its clocks; starting it again registers new ones. pcm1681 is not unbound in between: fw_devlink can't link it to q6prmcc, since that node has no device until the DSP is up, so the supplier link goes to the remoteproc device, which stays bound across the restart. pcm1681 is left with a handle to the orphaned clk, and the first runtime resume after the restart fails: pcm1681 0-004c: Failed to enable sck: -6 Reproduce with: echo stop > /sys/class/remoteproc/remoteproc1/state echo start > /sys/class/remoteproc/remoteproc1/state speaker-test -D plughw:0,0 -t sine -l 1 Even with a fresh handle the DAC stays silent, because the assigned-clock-rates (12.288 MHz) are applied by the i2c core only once, before probe, and the re-registered provider comes back at its default 19.2 MHz. The sound card, on the other hand, is torn down and re-created on an ADSP restart. So what works for me is to move the clock handling into the component .probe/.remove callbacks: clk_get_optional(), then of_clk_set_defaults() to re-apply the assigned rate, enable, settle, regcache_sync() and enable runtime PM in .probe; and the reverse plus clk_put() in .remove. The i2c probe then only creates the regmap, in cache-only mode until sck is running, and registers the component. Shawn